top_7279.tan.qmsg

AD0820小程序

{ "Info" "ITDB_TSU_RESULT" "U7279:inst\|FPGA_7279:inst3\|seg_cnt\[0\] KEY7279 SYS_CLK 4.131 ns register " "Info: tsu for register \"U7279:inst\|FPGA_7279:inst3\|seg_cnt\[0\]\" (data pin = \"KEY7279\", clock pin = \"SYS_CLK\") is 4.131 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.529 ns + Longest pin register " "Info: + Longest pin to register delay is 12.529 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns KEY7279 1 PIN PIN_159 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_159; Fanout = 8; PIN Node = 'KEY7279'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { KEY7279 } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 328 120 288 344 "KEY7279" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.495 ns) + CELL(0.114 ns) 10.078 ns U7279:inst\|FPGA_7279:inst3\|seg_cnt\[2\]~3 2 COMB LC_X30_Y12_N6 10 " "Info: 2: + IC(8.495 ns) + CELL(0.114 ns) = 10.078 ns; Loc. = LC_X30_Y12_N6; Fanout = 10; COMB Node = 'U7279:inst\|FPGA_7279:inst3\|seg_cnt\[2\]~3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.609 ns" { KEY7279 U7279:inst|FPGA_7279:inst3|seg_cnt[2]~3 } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.584 ns) + CELL(0.867 ns) 12.529 ns U7279:inst\|FPGA_7279:inst3\|seg_cnt\[0\] 3 REG LC_X29_Y14_N9 11 " "Info: 3: + IC(1.584 ns) + CELL(0.867 ns) = 12.529 ns; Loc. = LC_X29_Y14_N9; Fanout = 11; REG Node = 'U7279:inst\|FPGA_7279:inst3\|seg_cnt\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "2.451 ns" { U7279:inst|FPGA_7279:inst3|seg_cnt[2]~3 U7279:inst|FPGA_7279:inst3|seg_cnt[0] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.450 ns ( 19.55 % ) " "Info: Total cell delay = 2.450 ns ( 19.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.079 ns ( 80.45 % ) " "Info: Total interconnect delay = 10.079 ns ( 80.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "12.529 ns" { KEY7279 U7279:inst|FPGA_7279:inst3|seg_cnt[2]~3 U7279:inst|FPGA_7279:inst3|seg_cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.529 ns" { KEY7279 KEY7279~out0 U7279:inst|FPGA_7279:inst3|seg_cnt[2]~3 U7279:inst|FPGA_7279:inst3|seg_cnt[0] } { 0.000ns 0.000ns 8.495ns 1.584ns } { 0.000ns 1.469ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 8.435 ns - Shortest register " "Info: - Shortest clock path from clock \"SYS_CLK\" to destination register is 8.435 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 74 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 74; CLK Node = 'SYS_CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 104 48 216 120 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns U7279:inst\|div:inst1\|clk_tmp 2 REG LC_X15_Y13_N2 68 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X15_Y13_N2; Fanout = 68; REG Node = 'U7279:inst\|div:inst1\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.965 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.290 ns) + CELL(0.711 ns) 8.435 ns U7279:inst\|FPGA_7279:inst3\|seg_cnt\[0\] 3 REG LC_X29_Y14_N9 11 " "Info: 3: + IC(4.290 ns) + CELL(0.711 ns) = 8.435 ns; Loc. = LC_X29_Y14_N9; Fanout = 11; REG Node = 'U7279:inst\|FPGA_7279:inst3\|seg_cnt\[0\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "5.001 ns" { U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|seg_cnt[0] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 36.93 % ) " "Info: Total cell delay = 3.115 ns ( 36.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.320 ns ( 63.07 % ) " "Info: Total interconnect delay = 5.320 ns ( 63.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.435 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|seg_cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.435 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|seg_cnt[0] } { 0.000ns 0.000ns 1.030ns 4.290ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "12.529 ns" { KEY7279 U7279:inst|FPGA_7279:inst3|seg_cnt[2]~3 U7279:inst|FPGA_7279:inst3|seg_cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.529 ns" { KEY7279 KEY7279~out0 U7279:inst|FPGA_7279:inst3|seg_cnt[2]~3 U7279:inst|FPGA_7279:inst3|seg_cnt[0] } { 0.000ns 0.000ns 8.495ns 1.584ns } { 0.000ns 1.469ns 0.114ns 0.867ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.435 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|seg_cnt[0] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.435 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|seg_cnt[0] } { 0.000ns 0.000ns 1.030ns 4.290ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SYS_CLK DAT7279 U7279:inst\|FPGA_7279:inst3\|process0~1 15.074 ns register " "Info: tco from clock \"SYS_CLK\" to destination pin \"DAT7279\" through register \"U7279:inst\|FPGA_7279:inst3\|process0~1\" is 15.074 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 8.373 ns + Longest register " "Info: + Longest clock path from clock \"SYS_CLK\" to source register is 8.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 74 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 74; CLK Node = 'SYS_CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 104 48 216 120 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns U7279:inst\|div:inst1\|clk_tmp 2 REG LC_X15_Y13_N2 68 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X15_Y13_N2; Fanout = 68; REG Node = 'U7279:inst\|div:inst1\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.965 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.228 ns) + CELL(0.711 ns) 8.373 ns U7279:inst\|FPGA_7279:inst3\|process0~1 3 REG LC_X29_Y12_N6 1 " "Info: 3: + IC(4.228 ns) + CELL(0.711 ns) = 8.373 ns; Loc. = LC_X29_Y12_N6; Fanout = 1; REG Node = 'U7279:inst\|FPGA_7279:inst3\|process0~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "4.939 ns" { U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|process0~1 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.20 % ) " "Info: Total cell delay = 3.115 ns ( 37.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.258 ns ( 62.80 % ) " "Info: Total interconnect delay = 5.258 ns ( 62.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.373 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|process0~1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.373 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|process0~1 } { 0.000ns 0.000ns 1.030ns 4.228ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.477 ns + Longest register pin " "Info: + Longest register to pin delay is 6.477 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns U7279:inst\|FPGA_7279:inst3\|process0~1 1 REG LC_X29_Y12_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y12_N6; Fanout = 1; REG Node = 'U7279:inst\|FPGA_7279:inst3\|process0~1'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { U7279:inst|FPGA_7279:inst3|process0~1 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.403 ns) + CELL(2.074 ns) 6.477 ns DAT7279 2 PIN PIN_158 0 " "Info: 2: + IC(4.403 ns) + CELL(2.074 ns) = 6.477 ns; Loc. = PIN_158; Fanout = 0; PIN Node = 'DAT7279'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "6.477 ns" { U7279:inst|FPGA_7279:inst3|process0~1 DAT7279 } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 136 912 1088 152 "DAT7279" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.074 ns ( 32.02 % ) " "Info: Total cell delay = 2.074 ns ( 32.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.403 ns ( 67.98 % ) " "Info: Total interconnect delay = 4.403 ns ( 67.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "6.477 ns" { U7279:inst|FPGA_7279:inst3|process0~1 DAT7279 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.477 ns" { U7279:inst|FPGA_7279:inst3|process0~1 DAT7279 } { 0.000ns 4.403ns } { 0.000ns 2.074ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.373 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|process0~1 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.373 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|process0~1 } { 0.000ns 0.000ns 1.030ns 4.228ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "6.477 ns" { U7279:inst|FPGA_7279:inst3|process0~1 DAT7279 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "6.477 ns" { U7279:inst|FPGA_7279:inst3|process0~1 DAT7279 } { 0.000ns 4.403ns } { 0.000ns 2.074ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\] SYS_RST_N SYS_CLK 4.790 ns register " "Info: th for register \"U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\]\" (data pin = \"SYS_RST_N\", clock pin = \"SYS_CLK\") is 4.790 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 8.375 ns + Longest register " "Info: + Longest clock path from clock \"SYS_CLK\" to destination register is 8.375 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 74 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 74; CLK Node = 'SYS_CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 104 48 216 120 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns U7279:inst\|div:inst1\|clk_tmp 2 REG LC_X15_Y13_N2 68 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X15_Y13_N2; Fanout = 68; REG Node = 'U7279:inst\|div:inst1\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.965 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.230 ns) + CELL(0.711 ns) 8.375 ns U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\] 3 REG LC_X30_Y10_N8 8 " "Info: 3: + IC(4.230 ns) + CELL(0.711 ns) = 8.375 ns; Loc. = LC_X30_Y10_N8; Fanout = 8; REG Node = 'U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "4.941 ns" { U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 37.19 % ) " "Info: Total cell delay = 3.115 ns ( 37.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.260 ns ( 62.81 % ) " "Info: Total interconnect delay = 5.260 ns ( 62.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.375 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.375 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } { 0.000ns 0.000ns 1.030ns 4.230ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_RST_N 1 PIN PIN_131 129 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_131; Fanout = 129; PIN Node = 'SYS_RST_N'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { SYS_RST_N } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 120 48 216 136 "SYS_RST_N" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(0.292 ns) 2.854 ns U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\]~333 2 COMB LC_X30_Y10_N6 3 " "Info: 2: + IC(1.093 ns) + CELL(0.292 ns) = 2.854 ns; Loc. = LC_X30_Y10_N6; Fanout = 3; COMB Node = 'U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\]~333'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.385 ns" { SYS_RST_N U7279:inst|FPGA_7279:inst3|scmd_cnt[2]~333 } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.309 ns) 3.600 ns U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\] 3 REG LC_X30_Y10_N8 8 " "Info: 3: + IC(0.437 ns) + CELL(0.309 ns) = 3.600 ns; Loc. = LC_X30_Y10_N8; Fanout = 8; REG Node = 'U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "0.746 ns" { U7279:inst|FPGA_7279:inst3|scmd_cnt[2]~333 U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.070 ns ( 57.50 % ) " "Info: Total cell delay = 2.070 ns ( 57.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.530 ns ( 42.50 % ) " "Info: Total interconnect delay = 1.530 ns ( 42.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "3.600 ns" { SYS_RST_N U7279:inst|FPGA_7279:inst3|scmd_cnt[2]~333 U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.600 ns" { SYS_RST_N SYS_RST_N~out0 U7279:inst|FPGA_7279:inst3|scmd_cnt[2]~333 U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } { 0.000ns 0.000ns 1.093ns 0.437ns } { 0.000ns 1.469ns 0.292ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.375 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.375 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } { 0.000ns 0.000ns 1.030ns 4.230ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "3.600 ns" { SYS_RST_N U7279:inst|FPGA_7279:inst3|scmd_cnt[2]~333 U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.600 ns" { SYS_RST_N SYS_RST_N~out0 U7279:inst|FPGA_7279:inst3|scmd_cnt[2]~333 U7279:inst|FPGA_7279:inst3|scmd_cnt[2] } { 0.000ns 0.000ns 1.093ns 0.437ns } { 0.000ns 1.469ns 0.292ns 0.309ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 17 23:10:11 2008 " "Info: Processing ended: Sat May 17 23:10:11 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}