top_7279.tan.qmsg

AD0820小程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div:inst2\|clk_tmp " "Info: Detected ripple clock \"div:inst2\|clk_tmp\" as buffer" {  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "div:inst2\|clk_tmp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "U7279:inst\|div:inst1\|clk_tmp " "Info: Detected ripple clock \"U7279:inst\|div:inst1\|clk_tmp\" as buffer" {  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "U7279:inst\|div:inst1\|clk_tmp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SYS_CLK register U7279:inst\|Display8:inst5\|WR_N register U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[1\] 50.49 MHz 19.804 ns Internal " "Info: Clock \"SYS_CLK\" has Internal fmax of 50.49 MHz between source register \"U7279:inst\|Display8:inst5\|WR_N\" and destination register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[1\]\" (period= 19.804 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.108 ns + Longest register register " "Info: + Longest register to register delay is 5.108 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns U7279:inst\|Display8:inst5\|WR_N 1 REG LC_X28_Y15_N2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y15_N2; Fanout = 5; REG Node = 'U7279:inst\|Display8:inst5\|WR_N'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { U7279:inst|Display8:inst5|WR_N } "NODE_NAME" } "" } } { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.442 ns) 1.174 ns U7279:inst\|FPGA_7279:inst3\|Decoder~211 2 COMB LC_X29_Y15_N7 8 " "Info: 2: + IC(0.732 ns) + CELL(0.442 ns) = 1.174 ns; Loc. = LC_X29_Y15_N7; Fanout = 8; COMB Node = 'U7279:inst\|FPGA_7279:inst3\|Decoder~211'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.174 ns" { U7279:inst|Display8:inst5|WR_N U7279:inst|FPGA_7279:inst3|Decoder~211 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.525 ns) + CELL(0.590 ns) 2.289 ns U7279:inst\|FPGA_7279:inst3\|Decoder~213 3 COMB LC_X29_Y15_N3 7 " "Info: 3: + IC(0.525 ns) + CELL(0.590 ns) = 2.289 ns; Loc. = LC_X29_Y15_N3; Fanout = 7; COMB Node = 'U7279:inst\|FPGA_7279:inst3\|Decoder~213'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.115 ns" { U7279:inst|FPGA_7279:inst3|Decoder~211 U7279:inst|FPGA_7279:inst3|Decoder~213 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.952 ns) + CELL(0.867 ns) 5.108 ns U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[1\] 4 REG LC_X30_Y16_N1 1 " "Info: 4: + IC(1.952 ns) + CELL(0.867 ns) = 5.108 ns; Loc. = LC_X30_Y16_N1; Fanout = 1; REG Node = 'U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "2.819 ns" { U7279:inst|FPGA_7279:inst3|Decoder~213 U7279:inst|FPGA_7279:inst3|data_7279[3][1] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.899 ns ( 37.18 % ) " "Info: Total cell delay = 1.899 ns ( 37.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.209 ns ( 62.82 % ) " "Info: Total interconnect delay = 3.209 ns ( 62.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "5.108 ns" { U7279:inst|Display8:inst5|WR_N U7279:inst|FPGA_7279:inst3|Decoder~211 U7279:inst|FPGA_7279:inst3|Decoder~213 U7279:inst|FPGA_7279:inst3|data_7279[3][1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.108 ns" { U7279:inst|Display8:inst5|WR_N U7279:inst|FPGA_7279:inst3|Decoder~211 U7279:inst|FPGA_7279:inst3|Decoder~213 U7279:inst|FPGA_7279:inst3|data_7279[3][1] } { 0.000ns 0.732ns 0.525ns 1.952ns } { 0.000ns 0.442ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.533 ns - Smallest " "Info: - Smallest clock skew is -4.533 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 3.186 ns + Shortest register " "Info: + Shortest clock path from clock \"SYS_CLK\" to destination register is 3.186 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 74 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 74; CLK Node = 'SYS_CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 104 48 216 120 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.711 ns) 3.186 ns U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[1\] 2 REG LC_X30_Y16_N1 1 " "Info: 2: + IC(1.006 ns) + CELL(0.711 ns) = 3.186 ns; Loc. = LC_X30_Y16_N1; Fanout = 1; REG Node = 'U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.717 ns" { SYS_CLK U7279:inst|FPGA_7279:inst3|data_7279[3][1] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.42 % ) " "Info: Total cell delay = 2.180 ns ( 68.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.006 ns ( 31.58 % ) " "Info: Total interconnect delay = 1.006 ns ( 31.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "3.186 ns" { SYS_CLK U7279:inst|FPGA_7279:inst3|data_7279[3][1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.186 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|FPGA_7279:inst3|data_7279[3][1] } { 0.000ns 0.000ns 1.006ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 7.719 ns - Longest register " "Info: - Longest clock path from clock \"SYS_CLK\" to source register is 7.719 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 74 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 74; CLK Node = 'SYS_CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 104 48 216 120 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div:inst2\|clk_tmp 2 REG LC_X8_Y13_N9 28 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N9; Fanout = 28; REG Node = 'div:inst2\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.965 ns" { SYS_CLK div:inst2|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.574 ns) + CELL(0.711 ns) 7.719 ns U7279:inst\|Display8:inst5\|WR_N 3 REG LC_X28_Y15_N2 5 " "Info: 3: + IC(3.574 ns) + CELL(0.711 ns) = 7.719 ns; Loc. = LC_X28_Y15_N2; Fanout = 5; REG Node = 'U7279:inst\|Display8:inst5\|WR_N'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "4.285 ns" { div:inst2|clk_tmp U7279:inst|Display8:inst5|WR_N } "NODE_NAME" } "" } } { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.35 % ) " "Info: Total cell delay = 3.115 ns ( 40.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.604 ns ( 59.65 % ) " "Info: Total interconnect delay = 4.604 ns ( 59.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "7.719 ns" { SYS_CLK div:inst2|clk_tmp U7279:inst|Display8:inst5|WR_N } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.719 ns" { SYS_CLK SYS_CLK~out0 div:inst2|clk_tmp U7279:inst|Display8:inst5|WR_N } { 0.000ns 0.000ns 1.030ns 3.574ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "3.186 ns" { SYS_CLK U7279:inst|FPGA_7279:inst3|data_7279[3][1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.186 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|FPGA_7279:inst3|data_7279[3][1] } { 0.000ns 0.000ns 1.006ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "7.719 ns" { SYS_CLK div:inst2|clk_tmp U7279:inst|Display8:inst5|WR_N } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.719 ns" { SYS_CLK SYS_CLK~out0 div:inst2|clk_tmp U7279:inst|Display8:inst5|WR_N } { 0.000ns 0.000ns 1.030ns 3.574ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 9 -1 0 } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "5.108 ns" { U7279:inst|Display8:inst5|WR_N U7279:inst|FPGA_7279:inst3|Decoder~211 U7279:inst|FPGA_7279:inst3|Decoder~213 U7279:inst|FPGA_7279:inst3|data_7279[3][1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "5.108 ns" { U7279:inst|Display8:inst5|WR_N U7279:inst|FPGA_7279:inst3|Decoder~211 U7279:inst|FPGA_7279:inst3|Decoder~213 U7279:inst|FPGA_7279:inst3|data_7279[3][1] } { 0.000ns 0.732ns 0.525ns 1.952ns } { 0.000ns 0.442ns 0.590ns 0.867ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "3.186 ns" { SYS_CLK U7279:inst|FPGA_7279:inst3|data_7279[3][1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.186 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|FPGA_7279:inst3|data_7279[3][1] } { 0.000ns 0.000ns 1.006ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "7.719 ns" { SYS_CLK div:inst2|clk_tmp U7279:inst|Display8:inst5|WR_N } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.719 ns" { SYS_CLK SYS_CLK~out0 div:inst2|clk_tmp U7279:inst|Display8:inst5|WR_N } { 0.000ns 0.000ns 1.030ns 3.574ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "SYS_CLK 52 " "Warning: Circuit may not operate. Detected 52 non-operational path(s) clocked by clock \"SYS_CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "U7279:inst\|FPGA_7279:inst3\|data_7279\[7\]\[1\] U7279:inst\|FPGA_7279:inst3\|data_tmp\[1\] SYS_CLK 3.937 ns " "Info: Found hold time violation between source  pin or register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[7\]\[1\]\" and destination pin or register \"U7279:inst\|FPGA_7279:inst3\|data_tmp\[1\]\" for clock \"SYS_CLK\" (Hold time is 3.937 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.258 ns + Largest " "Info: + Largest clock skew is 5.258 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK destination 8.435 ns + Longest register " "Info: + Longest clock path from clock \"SYS_CLK\" to destination register is 8.435 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 74 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 74; CLK Node = 'SYS_CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 104 48 216 120 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns U7279:inst\|div:inst1\|clk_tmp 2 REG LC_X15_Y13_N2 68 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X15_Y13_N2; Fanout = 68; REG Node = 'U7279:inst\|div:inst1\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.965 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp } "NODE_NAME" } "" } } { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.290 ns) + CELL(0.711 ns) 8.435 ns U7279:inst\|FPGA_7279:inst3\|data_tmp\[1\] 3 REG LC_X29_Y14_N5 1 " "Info: 3: + IC(4.290 ns) + CELL(0.711 ns) = 8.435 ns; Loc. = LC_X29_Y14_N5; Fanout = 1; REG Node = 'U7279:inst\|FPGA_7279:inst3\|data_tmp\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "5.001 ns" { U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|data_tmp[1] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 36.93 % ) " "Info: Total cell delay = 3.115 ns ( 36.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.320 ns ( 63.07 % ) " "Info: Total interconnect delay = 5.320 ns ( 63.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.435 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|data_tmp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.435 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|data_tmp[1] } { 0.000ns 0.000ns 1.030ns 4.290ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYS_CLK source 3.177 ns - Shortest register " "Info: - Shortest clock path from clock \"SYS_CLK\" to source register is 3.177 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYS_CLK 1 CLK PIN_153 74 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 74; CLK Node = 'SYS_CLK'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { SYS_CLK } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 104 48 216 120 "SYS_CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.997 ns) + CELL(0.711 ns) 3.177 ns U7279:inst\|FPGA_7279:inst3\|data_7279\[7\]\[1\] 2 REG LC_X29_Y14_N1 1 " "Info: 2: + IC(0.997 ns) + CELL(0.711 ns) = 3.177 ns; Loc. = LC_X29_Y14_N1; Fanout = 1; REG Node = 'U7279:inst\|FPGA_7279:inst3\|data_7279\[7\]\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.708 ns" { SYS_CLK U7279:inst|FPGA_7279:inst3|data_7279[7][1] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 68.62 % ) " "Info: Total cell delay = 2.180 ns ( 68.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 31.38 % ) " "Info: Total interconnect delay = 0.997 ns ( 31.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "3.177 ns" { SYS_CLK U7279:inst|FPGA_7279:inst3|data_7279[7][1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.177 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|FPGA_7279:inst3|data_7279[7][1] } { 0.000ns 0.000ns 0.997ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.435 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|data_tmp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.435 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|data_tmp[1] } { 0.000ns 0.000ns 1.030ns 4.290ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "3.177 ns" { SYS_CLK U7279:inst|FPGA_7279:inst3|data_7279[7][1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.177 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|FPGA_7279:inst3|data_7279[7][1] } { 0.000ns 0.000ns 0.997ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.112 ns - Shortest register register " "Info: - Shortest register to register delay is 1.112 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns U7279:inst\|FPGA_7279:inst3\|data_7279\[7\]\[1\] 1 REG LC_X29_Y14_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y14_N1; Fanout = 1; REG Node = 'U7279:inst\|FPGA_7279:inst3\|data_7279\[7\]\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { U7279:inst|FPGA_7279:inst3|data_7279[7][1] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 0.378 ns U7279:inst\|FPGA_7279:inst3\|Mux~373 2 COMB LC_X29_Y14_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(0.378 ns) = 0.378 ns; Loc. = LC_X29_Y14_N1; Fanout = 1; COMB Node = 'U7279:inst\|FPGA_7279:inst3\|Mux~373'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "0.378 ns" { U7279:inst|FPGA_7279:inst3|data_7279[7][1] U7279:inst|FPGA_7279:inst3|Mux~373 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.425 ns) + CELL(0.309 ns) 1.112 ns U7279:inst\|FPGA_7279:inst3\|data_tmp\[1\] 3 REG LC_X29_Y14_N5 1 " "Info: 3: + IC(0.425 ns) + CELL(0.309 ns) = 1.112 ns; Loc. = LC_X29_Y14_N5; Fanout = 1; REG Node = 'U7279:inst\|FPGA_7279:inst3\|data_tmp\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "0.734 ns" { U7279:inst|FPGA_7279:inst3|Mux~373 U7279:inst|FPGA_7279:inst3|data_tmp[1] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.687 ns ( 61.78 % ) " "Info: Total cell delay = 0.687 ns ( 61.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.425 ns ( 38.22 % ) " "Info: Total interconnect delay = 0.425 ns ( 38.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.112 ns" { U7279:inst|FPGA_7279:inst3|data_7279[7][1] U7279:inst|FPGA_7279:inst3|Mux~373 U7279:inst|FPGA_7279:inst3|data_tmp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.112 ns" { U7279:inst|FPGA_7279:inst3|data_7279[7][1] U7279:inst|FPGA_7279:inst3|Mux~373 U7279:inst|FPGA_7279:inst3|data_tmp[1] } { 0.000ns 0.000ns 0.425ns } { 0.000ns 0.378ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "8.435 ns" { SYS_CLK U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|data_tmp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.435 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|div:inst1|clk_tmp U7279:inst|FPGA_7279:inst3|data_tmp[1] } { 0.000ns 0.000ns 1.030ns 4.290ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "3.177 ns" { SYS_CLK U7279:inst|FPGA_7279:inst3|data_7279[7][1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.177 ns" { SYS_CLK SYS_CLK~out0 U7279:inst|FPGA_7279:inst3|data_7279[7][1] } { 0.000ns 0.000ns 0.997ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "1.112 ns" { U7279:inst|FPGA_7279:inst3|data_7279[7][1] U7279:inst|FPGA_7279:inst3|Mux~373 U7279:inst|FPGA_7279:inst3|data_tmp[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "1.112 ns" { U7279:inst|FPGA_7279:inst3|data_7279[7][1] U7279:inst|FPGA_7279:inst3|Mux~373 U7279:inst|FPGA_7279:inst3|data_tmp[1] } { 0.000ns 0.000ns 0.425ns } { 0.000ns 0.378ns 0.309ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}