top_7279.fit.qmsg

AD0820小程序

{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.682 ns register register " "Info: Estimated most critical path is register to register delay of 3.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns U7279:inst\|Display8:inst5\|WR_N 1 REG LAB_X28_Y15 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X28_Y15; Fanout = 5; REG Node = 'U7279:inst\|Display8:inst5\|WR_N'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { U7279:inst|Display8:inst5|WR_N } "NODE_NAME" } "" } } { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.590 ns) 0.961 ns U7279:inst\|FPGA_7279:inst3\|Decoder~211 2 COMB LAB_X29_Y15 8 " "Info: 2: + IC(0.371 ns) + CELL(0.590 ns) = 0.961 ns; Loc. = LAB_X29_Y15; Fanout = 8; COMB Node = 'U7279:inst\|FPGA_7279:inst3\|Decoder~211'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "0.961 ns" { U7279:inst|Display8:inst5|WR_N U7279:inst|FPGA_7279:inst3|Decoder~211 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.603 ns) + CELL(0.114 ns) 1.678 ns U7279:inst\|FPGA_7279:inst3\|Decoder~213 3 COMB LAB_X29_Y15 7 " "Info: 3: + IC(0.603 ns) + CELL(0.114 ns) = 1.678 ns; Loc. = LAB_X29_Y15; Fanout = 7; COMB Node = 'U7279:inst\|FPGA_7279:inst3\|Decoder~213'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "0.717 ns" { U7279:inst|FPGA_7279:inst3|Decoder~211 U7279:inst|FPGA_7279:inst3|Decoder~213 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.137 ns) + CELL(0.867 ns) 3.682 ns U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[5\] 4 REG LAB_X30_Y16 1 " "Info: 4: + IC(1.137 ns) + CELL(0.867 ns) = 3.682 ns; Loc. = LAB_X30_Y16; Fanout = 1; REG Node = 'U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[5\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "2.004 ns" { U7279:inst|FPGA_7279:inst3|Decoder~213 U7279:inst|FPGA_7279:inst3|data_7279[3][5] } "NODE_NAME" } "" } } { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.571 ns ( 42.67 % ) " "Info: Total cell delay = 1.571 ns ( 42.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.111 ns ( 57.33 % ) " "Info: Total interconnect delay = 2.111 ns ( 57.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "3.682 ns" { U7279:inst|Display8:inst5|WR_N U7279:inst|FPGA_7279:inst3|Decoder~211 U7279:inst|FPGA_7279:inst3|Decoder~213 U7279:inst|FPGA_7279:inst3|data_7279[3][5] } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "U7279:inst\|FPGA_7279:inst3\|process0~1 " "Info: Following pins have the same output enable: U7279:inst\|FPGA_7279:inst3\|process0~1" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional DAT7279 LVTTL " "Info: Type bidirectional pin DAT7279 uses the LVTTL I/O standard" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 136 912 1088 152 "DAT7279" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DAT7279" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top_7279" "UNKNOWN" "V1" "E:/vhdl code/HD7279/db/top_7279.quartus_db" { Floorplan "E:/vhdl code/HD7279/" "" "" { DAT7279 } "NODE_NAME" } "" } } { "E:/vhdl code/HD7279/top_7279.fld" "" { Floorplan "E:/vhdl code/HD7279/top_7279.fld" "" "" { DAT7279 } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 17 23:10:01 2008 " "Info: Processing ended: Sat May 17 23:10:01 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}