top_7279.fit.qmsg

AD0820小程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 17 23:09:49 2008 " "Info: Processing started: Sat May 17 23:09:49 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off top_7279 -c top_7279 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off top_7279 -c top_7279" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "top_7279 EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"top_7279\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_TOP" "" "Info: Selected Migration Device List" { { "Info" "IMPP_MPP_DEV_MIG_DEVICE_LIST_MESSAGE_SUB" "EP1C6Q240C8 " "Info: Selected EP1C6Q240C8 for migration" {  } {  } 0 0 "Selected %1!s! for migration" 0 0}  } {  } 0 0 "Selected Migration Device List" 0 0}
{ "Info" "IMPP_MPP_NUM_MIGRATABLE_IO" "227 " "Info: Selected migration device list is legal with 227 total of migratable pins" {  } {  } 0 0 "Selected migration device list is legal with %1!d! total of migratable pins" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "SYS_CLK Global clock in PIN 153 " "Info: Automatically promoted signal \"SYS_CLK\" to use Global clock in PIN 153" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 104 48 216 120 "SYS_CLK" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "U7279:inst\|div:inst1\|clk_tmp Global clock " "Info: Automatically promoted some destinations of signal \"U7279:inst\|div:inst1\|clk_tmp\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|div:inst1\|clk_tmp " "Info: Destination \"U7279:inst\|div:inst1\|clk_tmp\" may be non-global or may not use global clock" {  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "div:inst2\|clk_tmp Global clock " "Info: Automatically promoted some destinations of signal \"div:inst2\|clk_tmp\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "div:inst2\|clk_tmp " "Info: Destination \"div:inst2\|clk_tmp\" may be non-global or may not use global clock" {  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "SYS_RST_N Global clock in PIN 131 " "Info: Automatically promoted some destinations of signal \"SYS_RST_N\" to use Global clock in PIN 131" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|div:inst1\|clk_tmp " "Info: Destination \"U7279:inst\|div:inst1\|clk_tmp\" may be non-global or may not use global clock" {  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|FPGA_7279:inst3\|sdata_cnt\[2\]~426 " "Info: Destination \"U7279:inst\|FPGA_7279:inst3\|sdata_cnt\[2\]~426\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\]~333 " "Info: Destination \"U7279:inst\|FPGA_7279:inst3\|scmd_cnt\[2\]~333\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|FPGA_7279:inst3\|data_tmp1\[0\]~7 " "Info: Destination \"U7279:inst\|FPGA_7279:inst3\|data_tmp1\[0\]~7\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|FPGA_7279:inst3\|delay_cnt\[1\]~779 " "Info: Destination \"U7279:inst\|FPGA_7279:inst3\|delay_cnt\[1\]~779\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[7\]~46 " "Info: Destination \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[7\]~46\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|FPGA_7279:inst3\|seg_cnt\[2\]~3 " "Info: Destination \"U7279:inst\|FPGA_7279:inst3\|seg_cnt\[2\]~3\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|FPGA_7279:inst3\|state1.start_wr " "Info: Destination \"U7279:inst\|FPGA_7279:inst3\|state1.start_wr\" may be non-global or may not use global clock" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "div:inst2\|clk_tmp " "Info: Destination \"div:inst2\|clk_tmp\" may be non-global or may not use global clock" {  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "U7279:inst\|Display8:inst5\|A_BUS\[0\]~5 " "Info: Destination \"U7279:inst\|Display8:inst5\|A_BUS\[0\]~5\" may be non-global or may not use global clock" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 120 48 216 136 "SYS_RST_N" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}