top_7279.hier_info

AD0820小程序

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CS7279 <= U7279:inst.CS7279
SYS_CLK => U7279:inst.SYS_CLK
SYS_CLK => div:inst2.clk
SYS_RST_N => U7279:inst.SYS_RST_N
SYS_RST_N => div:inst2.clr
SYS_RST_N => KEYVALUE:inst1.RST_N
KEY7279 => U7279:inst.KEY7279
DAT7279 <= U7279:inst.DAT7279
CLK7279 <= U7279:inst.CLK7279


|top|U7279:inst
CS7279 <= FPGA_7279:inst3.CS7279
SYS_RST_N => div:inst.clr
SYS_RST_N => Display8:inst5.RST_N
SYS_RST_N => div:inst1.clr
SYS_RST_N => FPGA_7279:inst3.RST_N
SYS_CLK => div:inst.clk
SYS_CLK => div:inst1.clk
SYS_CLK => FPGA_7279:inst3.CLK
Din[0] => Display8:inst5.Din[0]
Din[1] => Display8:inst5.Din[1]
Din[2] => Display8:inst5.Din[2]
Din[3] => Display8:inst5.Din[3]
Din[4] => Display8:inst5.Din[4]
Din[5] => Display8:inst5.Din[5]
Din[6] => Display8:inst5.Din[6]
Din[7] => Display8:inst5.Din[7]
Din[8] => Display8:inst5.Din[8]
Din[9] => Display8:inst5.Din[9]
Din[10] => Display8:inst5.Din[10]
Din[11] => Display8:inst5.Din[11]
Din[12] => Display8:inst5.Din[12]
Din[13] => Display8:inst5.Din[13]
Din[14] => Display8:inst5.Din[14]
Din[15] => Display8:inst5.Din[15]
Din[16] => Display8:inst5.Din[16]
Din[17] => Display8:inst5.Din[17]
Din[18] => Display8:inst5.Din[18]
Din[19] => Display8:inst5.Din[19]
Din[20] => Display8:inst5.Din[20]
Din[21] => Display8:inst5.Din[21]
Din[22] => Display8:inst5.Din[22]
Din[23] => Display8:inst5.Din[23]
Din[24] => Display8:inst5.Din[24]
Din[25] => Display8:inst5.Din[25]
Din[26] => Display8:inst5.Din[26]
Din[27] => Display8:inst5.Din[27]
Din[28] => Display8:inst5.Din[28]
Din[29] => Display8:inst5.Din[29]
Din[30] => Display8:inst5.Din[30]
Din[31] => Display8:inst5.Din[31]
RD_N => FPGA_7279:inst3.RD_N
KEY7279 => FPGA_7279:inst3.KEY7279
DAT7279 <= FPGA_7279:inst3.DAT7279
CLK7279 <= FPGA_7279:inst3.CLK7279
KEY_EN <= FPGA_7279:inst3.KEY_EN
OUT7279[0] <= FPGA_7279:inst3.OUT7279[0]
OUT7279[1] <= FPGA_7279:inst3.OUT7279[1]
OUT7279[2] <= FPGA_7279:inst3.OUT7279[2]
OUT7279[3] <= FPGA_7279:inst3.OUT7279[3]
OUT7279[4] <= FPGA_7279:inst3.OUT7279[4]
OUT7279[5] <= FPGA_7279:inst3.OUT7279[5]
OUT7279[6] <= FPGA_7279:inst3.OUT7279[6]
OUT7279[7] <= FPGA_7279:inst3.OUT7279[7]


|top|U7279:inst|FPGA_7279:inst3
CLK => data_7279[0][6].CLK
CLK => data_7279[0][5].CLK
CLK => data_7279[0][4].CLK
CLK => data_7279[0][3].CLK
CLK => data_7279[0][2].CLK
CLK => data_7279[0][1].CLK
CLK => data_7279[0][0].CLK
CLK => data_7279[1][7].CLK
CLK => data_7279[1][6].CLK
CLK => data_7279[1][5].CLK
CLK => data_7279[1][4].CLK
CLK => data_7279[1][3].CLK
CLK => data_7279[1][2].CLK
CLK => data_7279[1][1].CLK
CLK => data_7279[1][0].CLK
CLK => data_7279[2][7].CLK
CLK => data_7279[2][6].CLK
CLK => data_7279[2][5].CLK
CLK => data_7279[2][4].CLK
CLK => data_7279[2][3].CLK
CLK => data_7279[2][2].CLK
CLK => data_7279[2][1].CLK
CLK => data_7279[2][0].CLK
CLK => data_7279[3][7].CLK
CLK => data_7279[3][6].CLK
CLK => data_7279[3][5].CLK
CLK => data_7279[3][4].CLK
CLK => data_7279[3][3].CLK
CLK => data_7279[3][2].CLK
CLK => data_7279[3][1].CLK
CLK => data_7279[3][0].CLK
CLK => data_7279[4][7].CLK
CLK => data_7279[4][6].CLK
CLK => data_7279[4][5].CLK
CLK => data_7279[4][4].CLK
CLK => data_7279[4][3].CLK
CLK => data_7279[4][2].CLK
CLK => data_7279[4][1].CLK
CLK => data_7279[4][0].CLK
CLK => data_7279[5][7].CLK
CLK => data_7279[5][6].CLK
CLK => data_7279[5][5].CLK
CLK => data_7279[5][4].CLK
CLK => data_7279[5][3].CLK
CLK => data_7279[5][2].CLK
CLK => data_7279[5][1].CLK
CLK => data_7279[5][0].CLK
CLK => data_7279[6][7].CLK
CLK => data_7279[6][6].CLK
CLK => data_7279[6][5].CLK
CLK => data_7279[6][4].CLK
CLK => data_7279[6][3].CLK
CLK => data_7279[6][2].CLK
CLK => data_7279[6][1].CLK
CLK => data_7279[6][0].CLK
CLK => data_7279[7][7].CLK
CLK => data_7279[7][6].CLK
CLK => data_7279[7][5].CLK
CLK => data_7279[7][4].CLK
CLK => data_7279[7][3].CLK
CLK => data_7279[7][2].CLK
CLK => data_7279[7][1].CLK
CLK => data_7279[7][0].CLK
CLK => data_7279[0][7].CLK
CLK => state1~9.IN1
RST_N => key_7279[7].ACLR
RST_N => key_7279[6].ACLR
RST_N => key_7279[5].ACLR
RST_N => key_7279[4].ACLR
RST_N => key_7279[3].ACLR
RST_N => key_7279[2].ACLR
RST_N => key_7279[1].ACLR
RST_N => key_7279[0].ACLR
RST_N => CS7279~reg0.PRESET
RST_N => CLK7279~reg0.ACLR
RST_N => DAT7279~reg0.ACLR
RST_N => process0~1.ACLR
RST_N => data_start.ACLR
RST_N => data_7279[0][6].ACLR
RST_N => data_7279[0][5].ACLR
RST_N => data_7279[0][4].ACLR
RST_N => data_7279[0][3].ACLR
RST_N => data_7279[0][2].ACLR
RST_N => data_7279[0][1].ACLR
RST_N => data_7279[0][0].ACLR
RST_N => data_7279[1][7].ACLR
RST_N => data_7279[1][6].ACLR
RST_N => data_7279[1][5].ACLR
RST_N => data_7279[1][4].ACLR
RST_N => data_7279[1][3].ACLR
RST_N => data_7279[1][2].ACLR
RST_N => data_7279[1][1].ACLR
RST_N => data_7279[1][0].ACLR
RST_N => data_7279[2][7].ACLR
RST_N => data_7279[2][6].ACLR
RST_N => data_7279[2][5].ACLR
RST_N => data_7279[2][4].ACLR
RST_N => data_7279[2][3].ACLR
RST_N => data_7279[2][2].ACLR
RST_N => data_7279[2][1].ACLR
RST_N => data_7279[2][0].ACLR
RST_N => data_7279[3][7].ACLR
RST_N => data_7279[3][6].ACLR
RST_N => data_7279[3][5].ACLR
RST_N => data_7279[3][4].ACLR
RST_N => data_7279[3][3].ACLR
RST_N => data_7279[3][2].ACLR
RST_N => data_7279[3][1].ACLR
RST_N => data_7279[3][0].ACLR
RST_N => data_7279[4][7].ACLR
RST_N => data_7279[4][6].ACLR
RST_N => data_7279[4][5].ACLR
RST_N => data_7279[4][4].ACLR
RST_N => data_7279[4][3].ACLR
RST_N => data_7279[4][2].ACLR
RST_N => data_7279[4][1].ACLR
RST_N => data_7279[4][0].ACLR
RST_N => data_7279[5][7].ACLR
RST_N => data_7279[5][6].ACLR
RST_N => data_7279[5][5].ACLR
RST_N => data_7279[5][4].ACLR
RST_N => data_7279[5][3].ACLR
RST_N => data_7279[5][2].ACLR
RST_N => data_7279[5][1].ACLR
RST_N => data_7279[5][0].ACLR
RST_N => data_7279[6][7].ACLR
RST_N => data_7279[6][6].ACLR
RST_N => data_7279[6][5].ACLR
RST_N => data_7279[6][4].ACLR
RST_N => data_7279[6][3].ACLR
RST_N => data_7279[6][2].ACLR
RST_N => data_7279[6][1].ACLR
RST_N => data_7279[6][0].ACLR
RST_N => data_7279[7][7].ACLR
RST_N => data_7279[7][6].ACLR
RST_N => data_7279[7][5].ACLR
RST_N => data_7279[7][4].ACLR
RST_N => data_7279[7][3].ACLR
RST_N => data_7279[7][2].ACLR
RST_N => data_7279[7][1].ACLR
RST_N => data_7279[7][0].ACLR
RST_N => state1~6.OUTPUTSELECT
RST_N => state1~7.OUTPUTSELECT
RST_N => state1~8.OUTPUTSELECT
RST_N => data_7279[0][7].ACLR
RST_N => key_flag~0.IN0
RST_N => delay_cnt[1].ENA
RST_N => delay_cnt[0].ENA
RST_N => scmd_cnt[2].ENA
RST_N => scmd_cnt[1].ENA
RST_N => scmd_cnt[0].ENA
RST_N => sdata_cnt[2].ENA
RST_N => sdata_cnt[1].ENA
RST_N => sdata_cnt[0].ENA
RST_N => state~18.IN1
CLK_S => key_7279[7].CLK
CLK_S => key_7279[6].CLK
CLK_S => key_7279[5].CLK
CLK_S => key_7279[4].CLK
CLK_S => key_7279[3].CLK
CLK_S => key_7279[2].CLK
CLK_S => key_7279[1].CLK
CLK_S => key_7279[0].CLK
CLK_S => CS7279~reg0.CLK
CLK_S => CLK7279~reg0.CLK
CLK_S => DAT7279~reg0.CLK
CLK_S => cmd_tmp[7].CLK
CLK_S => cmd_tmp[6].CLK
CLK_S => cmd_tmp[5].CLK
CLK_S => cmd_tmp[4].CLK
CLK_S => cmd_tmp[3].CLK
CLK_S => cmd_tmp[2].CLK
CLK_S => cmd_tmp[1].CLK
CLK_S => cmd_tmp[0].CLK
CLK_S => seg_cnt[2].CLK
CLK_S => seg_cnt[1].CLK
CLK_S => seg_cnt[0].CLK
CLK_S => data_tmp[7].CLK
CLK_S => data_tmp[6].CLK
CLK_S => data_tmp[5].CLK
CLK_S => data_tmp[4].CLK
CLK_S => data_tmp[3].CLK
CLK_S => data_tmp[2].CLK
CLK_S => data_tmp[1].CLK
CLK_S => data_tmp[0].CLK
CLK_S => delay_cnt[1].CLK
CLK_S => delay_cnt[0].CLK
CLK_S => scmd_cnt[2].CLK
CLK_S => scmd_cnt[1].CLK
CLK_S => scmd_cnt[0].CLK
CLK_S => sdata_cnt[2].CLK
CLK_S => sdata_cnt[1].CLK
CLK_S => sdata_cnt[0].CLK
CLK_S => key_7279_tmp[7].CLK
CLK_S => key_7279_tmp[6].CLK
CLK_S => key_7279_tmp[5].CLK
CLK_S => key_7279_tmp[4].CLK
CLK_S => key_7279_tmp[3].CLK
CLK_S => key_7279_tmp[2].CLK
CLK_S => key_7279_tmp[1].CLK
CLK_S => key_7279_tmp[0].CLK
CLK_S => process0~1.CLK
CLK_S => data_start.CLK
CLK_S => cmd_tmp1[7].CLK
CLK_S => cmd_tmp1[6].CLK
CLK_S => cmd_tmp1[5].CLK
CLK_S => cmd_tmp1[4].CLK
CLK_S => cmd_tmp1[3].CLK
CLK_S => cmd_tmp1[2].CLK
CLK_S => cmd_tmp1[1].CLK
CLK_S => cmd_tmp1[0].CLK
CLK_S => data_tmp1[7].CLK
CLK_S => data_tmp1[6].CLK
CLK_S => data_tmp1[5].CLK
CLK_S => data_tmp1[4].CLK
CLK_S => data_tmp1[3].CLK
CLK_S => data_tmp1[2].CLK
CLK_S => data_tmp1[1].CLK
CLK_S => data_tmp1[0].CLK
CLK_S => data_start_tmp.CLK
CLK_S => state~17.IN1
WR_N => state1~3.OUTPUTSELECT
WR_N => state1~4.OUTPUTSELECT
WR_N => state1~5.OUTPUTSELECT
WR_N => state1~0.OUTPUTSELECT
WR_N => state1~1.OUTPUTSELECT
WR_N => state1~2.OUTPUTSELECT
RD_N => key_flag~0.IN1
KEY_EN <= key_flag.DB_MAX_OUTPUT_PORT_TYPE
ADDR[0] => Decoder~1.IN2
ADDR[1] => Decoder~1.IN1
ADDR[2] => Decoder~1.IN0
D_BUS[0] => Equal~3.IN7
D_BUS[0] => Equal~4.IN7
D_BUS[0] => Equal~5.IN7
D_BUS[0] => Equal~6.IN7
D_BUS[0] => Equal~7.IN7
D_BUS[0] => Equal~8.IN7
D_BUS[0] => Equal~9.IN7
D_BUS[0] => Equal~10.IN7
D_BUS[0] => Equal~11.IN7
D_BUS[0] => Equal~12.IN7
D_BUS[0] => Equal~13.IN7
D_BUS[0] => Equal~14.IN7
D_BUS[0] => Equal~15.IN7
D_BUS[0] => Equal~16.IN7
D_BUS[0] => Equal~17.IN7
D_BUS[0] => Equal~18.IN7
D_BUS[0] => Equal~19.IN15
D_BUS[1] => Equal~3.IN6