top_7279.tan.rpt

AD0820小程序

+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; SYS_CLK         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SYS_CLK'                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                               ; To                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 50.49 MHz ( period = 19.804 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[3][1] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 5.108 ns                ;
; N/A                                     ; 50.49 MHz ( period = 19.804 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[3][2] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 5.108 ns                ;
; N/A                                     ; 50.49 MHz ( period = 19.804 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[3][6] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 5.108 ns                ;
; N/A                                     ; 50.49 MHz ( period = 19.804 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[3][4] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 5.108 ns                ;
; N/A                                     ; 50.49 MHz ( period = 19.804 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[3][5] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 5.108 ns                ;
; N/A                                     ; 51.66 MHz ( period = 19.358 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[4][3] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.810 ns                ;
; N/A                                     ; 51.66 MHz ( period = 19.358 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[4][1] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.810 ns                ;
; N/A                                     ; 52.03 MHz ( period = 19.218 ns )                    ; U7279:inst|Display8:inst5|D_BUS[0] ; U7279:inst|FPGA_7279:inst3|data_7279[4][3] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.730 ns                ;
; N/A                                     ; 52.11 MHz ( period = 19.192 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[6][0] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.793 ns                ;
; N/A                                     ; 52.11 MHz ( period = 19.192 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[6][1] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.793 ns                ;
; N/A                                     ; 52.11 MHz ( period = 19.192 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[6][2] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.793 ns                ;
; N/A                                     ; 52.11 MHz ( period = 19.192 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[6][6] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.793 ns                ;
; N/A                                     ; 52.11 MHz ( period = 19.192 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[6][4] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.793 ns                ;
; N/A                                     ; 52.11 MHz ( period = 19.192 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[6][5] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.793 ns                ;
; N/A                                     ; 52.45 MHz ( period = 19.064 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[1][3] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.738 ns                ;
; N/A                                     ; 52.45 MHz ( period = 19.064 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[1][0] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.738 ns                ;
; N/A                                     ; 52.45 MHz ( period = 19.064 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[1][1] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.738 ns                ;
; N/A                                     ; 52.45 MHz ( period = 19.064 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[1][2] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.738 ns                ;
; N/A                                     ; 52.45 MHz ( period = 19.064 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[1][6] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.738 ns                ;
; N/A                                     ; 52.45 MHz ( period = 19.064 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[1][4] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.738 ns                ;
; N/A                                     ; 53.02 MHz ( period = 18.860 ns )                    ; U7279:inst|Display8:inst5|D_BUS[2] ; U7279:inst|FPGA_7279:inst3|data_7279[4][3] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.551 ns                ;
; N/A                                     ; 53.65 MHz ( period = 18.638 ns )                    ; U7279:inst|Display8:inst5|D_BUS[3] ; U7279:inst|FPGA_7279:inst3|data_7279[4][3] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.440 ns                ;
; N/A                                     ; 53.92 MHz ( period = 18.546 ns )                    ; U7279:inst|Display8:inst5|WR_N     ; U7279:inst|FPGA_7279:inst3|data_7279[5][1] ; SYS_CLK    ; SYS_CLK  ; None                        ; None                      ; 4.479 ns                ;