keyvalue.vhd

AD0820小程序

-- Quartus VHDL Template
-- Clearable flipflop with enable

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY KEYVALUE IS
	PORT
	(	CLK,RST_N     :IN      STD_LOGIC; 
		RDKY_EN   :IN     STD_LOGIC;  --存在有效键值, 高电平为存在有效键值, 外部接口读走数据后变低
		RD_N      :OUT    STD_LOGIC;  --外部读信号
		D_KEY  	  :IN   STD_LOGIC_VECTOR(7 downto 0);   --读键值
		Q		: OUT	STD_LOGIC_VECTOR(31 downto 0)
	);	
END KEYVALUE;

ARCHITECTURE a OF KEYVALUE IS
	SIGNAL	key_7279	: STD_LOGIC_VECTOR(7 DOWNTO 0);	
	TYPE STATE_KEY IS (IDLE, START, STOP);
	SIGNAL state_ky: STATE_KEY;
BEGIN
	process(CLK,RST_N)
	begin
	if (RST_N = '0') then
		RD_N <= '1';	key_7279<= x"FF";			
	elsif CLK'EVENT AND CLK = '1' then
		case state_ky is
			when IDLE =>				
				if (RDKY_EN = '1') then
					state_ky <= START;
					RD_N <= '0';
				else
					key_7279<= D_KEY;
					RD_N <= '1';
				end if;
			when START =>				
				RD_N <= '1';
				state_ky <= STOP;
			when STOP =>				
				state_ky <= IDLE;
			when others =>	NULL;
		end case;		
		key_7279<= D_KEY;		
	end if;
end process;

process(CLK,key_7279)
	begin
	if CLK'EVENT AND CLK = '1' then
		case key_7279 is
			when "00000001" =>				
				Q<= "10100000000100100011010010000000";
			when "00000010" =>				
				Q<= "10110000000110110011010010000000";
			when "00000011" =>				
				Q<= "10110000000110110011010010000100";
			when others =>	NULL;
		end case;				
	end if;
end process;
	
END a;