display8.vhd

AD0820小程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY Display8 IS                                    
    PORT (
			CLK,RST_N   : IN STD_LOGIC; 
            Din   		: in STD_LOGIC_VECTOR(31 DOWNTO 0);  
			WR_N      	:OUT    STD_LOGIC;  --外部写信号
			
			A_BUS	  :OUT  STD_LOGIC_VECTOR(2 downto 0);  
			D_BUS  	  :OUT  STD_LOGIC_VECTOR(7 downto 0));
 END Display8;

ARCHITECTURE one OF Display8 IS
	signal dp		: std_logic;
    SIGNAL CNT8  :  STD_LOGIC_VECTOR(2 DOWNTO 0); 
	SIGNAL DISD	 :	STD_LOGIC_VECTOR(3 DOWNTO 0);--display data
	
	TYPE STATE_TYPE IS (IDLE, START, D_SETUP, D_SETUP1, D_WRITE, D_HOLD, WR_STOP);
	SIGNAL state: STATE_TYPE;
BEGIN

P1: PROCESS( CNT8 )
    BEGIN
        CASE  CNT8 IS
          WHEN "000" =>  DISD<= Din(3 downto 0); 
          WHEN "001" =>  DISD<= Din(7 downto 4); 
          WHEN "010" =>  DISD<= Din(11 downto 8);
          WHEN "011" =>  DISD<= Din(15 downto 12);
          WHEN "100" =>  DISD<= Din(19 downto 16);
          WHEN "101" =>  DISD<= Din(23 downto 20);
          WHEN "110" =>  DISD<= Din(27 downto 24);
          WHEN "111" =>  DISD<= Din(31 downto 28);
          WHEN OTHERS =>  NULL ;
        END CASE ;   
     END PROCESS P1;

dp <= '0';	--不显示小数点,写显示状态机
process(CLK,RST_N,CNT8)
	begin
	if (RST_N = '0') then
		WR_N <= '1';	D_BUS <= x"00";		CNT8<="000";	
		state <= IDLE; 	
	elsif( CLK'EVENT AND  CLK= '1')	then
		case state is
			when IDLE =>				
				WR_N <= '1';	A_BUS <= CNT8;
				state <= START;						
			when START =>
				D_BUS <= dp & "000" & DISD;--数据建立时间
				state <= D_SETUP;
			when D_SETUP =>		--两个时钟周期的建立时间
				WR_N <= '0'; CNT8 <= CNT8 + 1;
				state <= D_SETUP1;
			when D_SETUP1 =>
				state <= D_HOLD;
			when D_HOLD =>		--保持时间
				WR_N <= '1';	
				state <= WR_STOP;
			when WR_STOP =>	
				state <= IDLE;
			when others =>NULL;	
		end case;
	end if;
end process;

end;