top_7279.map.eqn

AD0820小程序

--F1_CNT8[0] is U7279:inst|Display8:inst5|CNT8[0]
--operation mode is normal

F1_CNT8[0]_lut_out = F1_CNT8[0] $ F1_state.d_setup;
F1_CNT8[0] = DFFEAS(F1_CNT8[0]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1_Q[28] is KEYVALUE:inst1|Q[28]
--operation mode is normal

C1_Q[28]_lut_out = C1_key_7279[0] # !C1_key_7279[1];
C1_Q[28] = DFFEAS(C1_Q[28]_lut_out, D3_clk_tmp, VCC, , C1L14, , , , );


--F1_CNT8[2] is U7279:inst|Display8:inst5|CNT8[2]
--operation mode is normal

F1_CNT8[2]_lut_out = F1_CNT8[2] $ (F1_CNT8[0] & F1_CNT8[1] & F1_state.d_setup);
F1_CNT8[2] = DFFEAS(F1_CNT8[2]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--F1_CNT8[1] is U7279:inst|Display8:inst5|CNT8[1]
--operation mode is normal

F1_CNT8[1]_lut_out = F1_CNT8[1] $ (F1_CNT8[0] & F1_state.d_setup);
F1_CNT8[1] = DFFEAS(F1_CNT8[1]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--D3_clk_tmp is div:inst2|clk_tmp
--operation mode is normal

D3_clk_tmp_lut_out = D3_clk_tmp $ (!D3L7 & (SYS_RST_N));
D3_clk_tmp = DFFEAS(D3_clk_tmp_lut_out, !SYS_CLK, VCC, , , , , , );


--F1_state.start is U7279:inst|Display8:inst5|state.start
--operation mode is normal

F1_state.start_lut_out = !F1_state.idle;
F1_state.start = DFFEAS(F1_state.start_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1_Q[2] is KEYVALUE:inst1|Q[2]
--operation mode is normal

C1_Q[2]_lut_out = !C1_key_7279[1] & !C1_key_7279[0];
C1_Q[2] = DFFEAS(C1_Q[2]_lut_out, D3_clk_tmp, VCC, , C1L14, , , , );


--F1_state.idle is U7279:inst|Display8:inst5|state.idle
--operation mode is normal

F1_state.idle_lut_out = !F1_state.wr_stop;
F1_state.idle = DFFEAS(F1_state.idle_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--F1L3 is U7279:inst|Display8:inst5|A_BUS[0]~5
--operation mode is normal

F1L3 = SYS_RST_N & (!F1_state.idle);


--F1_state.d_hold is U7279:inst|Display8:inst5|state.d_hold
--operation mode is normal

F1_state.d_hold_lut_out = F1_state.d_setup1;
F1_state.d_hold = DFFEAS(F1_state.d_hold_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--F1_state.d_setup is U7279:inst|Display8:inst5|state.d_setup
--operation mode is normal

F1_state.d_setup_lut_out = F1_state.start;
F1_state.d_setup = DFFEAS(F1_state.d_setup_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--E1_state1.idle is U7279:inst|FPGA_7279:inst3|state1.idle
--operation mode is normal

E1_state1.idle_lut_out = !E1_state1.stop & (F1_WR_N # E1_state1.idle);
E1_state1.idle = DFFEAS(E1_state1.idle_lut_out, !SYS_CLK, VCC, , SYS_RST_N, , , , );


--C1_key_7279[0] is KEYVALUE:inst1|key_7279[0]
--operation mode is normal

C1_key_7279[0]_lut_out = !E1_key_7279[0];
C1_key_7279[0] = DFFEAS(C1_key_7279[0]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1_key_7279[1] is KEYVALUE:inst1|key_7279[1]
--operation mode is normal

C1_key_7279[1]_lut_out = !E1_key_7279[1];
C1_key_7279[1] = DFFEAS(C1_key_7279[1]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1_key_7279[2] is KEYVALUE:inst1|key_7279[2]
--operation mode is normal

C1_key_7279[2]_lut_out = !E1_key_7279[2];
C1_key_7279[2] = DFFEAS(C1_key_7279[2]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1_key_7279[3] is KEYVALUE:inst1|key_7279[3]
--operation mode is normal

C1_key_7279[3]_lut_out = !E1_key_7279[3];
C1_key_7279[3] = DFFEAS(C1_key_7279[3]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1L12 is KEYVALUE:inst1|Q[2]~102
--operation mode is normal

C1L12 = !C1_key_7279[3] # !C1_key_7279[2];


--C1_key_7279[4] is KEYVALUE:inst1|key_7279[4]
--operation mode is normal

C1_key_7279[4]_lut_out = !E1_key_7279[4];
C1_key_7279[4] = DFFEAS(C1_key_7279[4]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1_key_7279[5] is KEYVALUE:inst1|key_7279[5]
--operation mode is normal

C1_key_7279[5]_lut_out = !E1_key_7279[5];
C1_key_7279[5] = DFFEAS(C1_key_7279[5]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1_key_7279[7] is KEYVALUE:inst1|key_7279[7]
--operation mode is normal

C1_key_7279[7]_lut_out = !E1_key_7279[7];
C1_key_7279[7] = DFFEAS(C1_key_7279[7]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1_key_7279[6] is KEYVALUE:inst1|key_7279[6]
--operation mode is normal

C1_key_7279[6]_lut_out = !E1_key_7279[6];
C1_key_7279[6] = DFFEAS(C1_key_7279[6]_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--C1L13 is KEYVALUE:inst1|Q[2]~103
--operation mode is normal

C1L13 = !C1_key_7279[6] # !C1_key_7279[7] # !C1_key_7279[5] # !C1_key_7279[4];


--C1L14 is KEYVALUE:inst1|Q[2]~104
--operation mode is normal

C1L14 = !C1L12 & !C1L13 & (!C1_key_7279[0] # !C1_key_7279[1]);


--D3_fre_N[2] is div:inst2|fre_N[2]
--operation mode is normal

D3_fre_N[2]_lut_out = !D3_fre_N[3] & (D3_fre_N[2] $ (D3_fre_N[1] & D3_fre_N[0]));
D3_fre_N[2] = DFFEAS(D3_fre_N[2]_lut_out, !SYS_CLK, SYS_RST_N, , , , , , );


--D3_fre_N[1] is div:inst2|fre_N[1]
--operation mode is normal

D3_fre_N[1]_lut_out = !D3_fre_N[3] & (D3_fre_N[1] $ D3_fre_N[0]);
D3_fre_N[1] = DFFEAS(D3_fre_N[1]_lut_out, !SYS_CLK, SYS_RST_N, , , , , , );


--D3_fre_N[0] is div:inst2|fre_N[0]
--operation mode is normal

D3_fre_N[0]_lut_out = !D3_fre_N[0] & (!D3_fre_N[2] & !D3_fre_N[1] # !D3_fre_N[3]);
D3_fre_N[0] = DFFEAS(D3_fre_N[0]_lut_out, !SYS_CLK, SYS_RST_N, , , , , , );


--D3_fre_N[3] is div:inst2|fre_N[3]
--operation mode is normal

D3_fre_N[3]_lut_out = D3_fre_N[3] & !D3_fre_N[2] & !D3_fre_N[1] & !D3_fre_N[0] # !D3_fre_N[3] & D3_fre_N[2] & D3_fre_N[1] & D3_fre_N[0];
D3_fre_N[3] = DFFEAS(D3_fre_N[3]_lut_out, !SYS_CLK, SYS_RST_N, , , , , , );


--D3L7 is div:inst2|LessThan~53
--operation mode is normal

D3L7 = !D3_fre_N[2] & !D3_fre_N[1] & !D3_fre_N[0] # !D3_fre_N[3];


--F1_state.wr_stop is U7279:inst|Display8:inst5|state.wr_stop
--operation mode is normal

F1_state.wr_stop_lut_out = F1_state.d_hold;
F1_state.wr_stop = DFFEAS(F1_state.wr_stop_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--F1_state.d_setup1 is U7279:inst|Display8:inst5|state.d_setup1
--operation mode is normal

F1_state.d_setup1_lut_out = F1_state.d_setup;
F1_state.d_setup1 = DFFEAS(F1_state.d_setup1_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--E1_state1.stop is U7279:inst|FPGA_7279:inst3|state1.stop
--operation mode is normal

E1_state1.stop_lut_out = E1_state1.start_wr & (!F1_WR_N);
E1_state1.stop = DFFEAS(E1_state1.stop_lut_out, !SYS_CLK, VCC, , SYS_RST_N, , , , );


--E1_key_7279[0] is U7279:inst|FPGA_7279:inst3|key_7279[0]
--operation mode is normal

E1_key_7279[0]_lut_out = E1_key_7279_tmp[0];
E1_key_7279[0] = DFFEAS(E1_key_7279[0]_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L138, , , , );


--E1_key_7279[1] is U7279:inst|FPGA_7279:inst3|key_7279[1]
--operation mode is normal

E1_key_7279[1]_lut_out = E1_key_7279_tmp[1];
E1_key_7279[1] = DFFEAS(E1_key_7279[1]_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L138, , , , );


--E1_key_7279[2] is U7279:inst|FPGA_7279:inst3|key_7279[2]
--operation mode is normal

E1_key_7279[2]_lut_out = E1_key_7279_tmp[2];
E1_key_7279[2] = DFFEAS(E1_key_7279[2]_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L138, , , , );


--E1_key_7279[3] is U7279:inst|FPGA_7279:inst3|key_7279[3]
--operation mode is normal

E1_key_7279[3]_lut_out = E1_key_7279_tmp[3];
E1_key_7279[3] = DFFEAS(E1_key_7279[3]_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L138, , , , );


--E1_key_7279[4] is U7279:inst|FPGA_7279:inst3|key_7279[4]
--operation mode is normal

E1_key_7279[4]_lut_out = E1_key_7279_tmp[4];
E1_key_7279[4] = DFFEAS(E1_key_7279[4]_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L138, , , , );


--E1_key_7279[5] is U7279:inst|FPGA_7279:inst3|key_7279[5]
--operation mode is normal

E1_key_7279[5]_lut_out = E1_key_7279_tmp[5];
E1_key_7279[5] = DFFEAS(E1_key_7279[5]_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L138, , , , );


--E1_key_7279[7] is U7279:inst|FPGA_7279:inst3|key_7279[7]
--operation mode is normal

E1_key_7279[7]_lut_out = E1_key_7279_tmp[7];
E1_key_7279[7] = DFFEAS(E1_key_7279[7]_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L138, , , , );


--E1_key_7279[6] is U7279:inst|FPGA_7279:inst3|key_7279[6]
--operation mode is normal

E1_key_7279[6]_lut_out = E1_key_7279_tmp[6];
E1_key_7279[6] = DFFEAS(E1_key_7279[6]_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L138, , , , );


--E1_key_7279_tmp[0] is U7279:inst|FPGA_7279:inst3|key_7279_tmp[0]
--operation mode is normal

E1_key_7279_tmp[0]_lut_out = E1L115 & A1L4 # !E1L115 & (E1_key_7279_tmp[0]);
E1_key_7279_tmp[0] = DFFEAS(E1_key_7279_tmp[0]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1L138 is U7279:inst|FPGA_7279:inst3|key_7279[7]~54
--operation mode is normal

E1L138 = E1_state.shift_key_high1 & !E1_sdata_cnt[2] & !E1L148 & !KEY7279;


--E1_key_7279_tmp[1] is U7279:inst|FPGA_7279:inst3|key_7279_tmp[1]
--operation mode is normal

E1_key_7279_tmp[1]_lut_out = E1L116 & A1L4 # !E1L116 & (E1_key_7279_tmp[1]);
E1_key_7279_tmp[1] = DFFEAS(E1_key_7279_tmp[1]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1_key_7279_tmp[2] is U7279:inst|FPGA_7279:inst3|key_7279_tmp[2]
--operation mode is normal

E1_key_7279_tmp[2]_lut_out = E1L117 & A1L4 # !E1L117 & (E1_key_7279_tmp[2]);
E1_key_7279_tmp[2] = DFFEAS(E1_key_7279_tmp[2]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1_key_7279_tmp[3] is U7279:inst|FPGA_7279:inst3|key_7279_tmp[3]
--operation mode is normal

E1_key_7279_tmp[3]_lut_out = E1L118 & A1L4 # !E1L118 & (E1_key_7279_tmp[3]);
E1_key_7279_tmp[3] = DFFEAS(E1_key_7279_tmp[3]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1_key_7279_tmp[4] is U7279:inst|FPGA_7279:inst3|key_7279_tmp[4]
--operation mode is normal

E1_key_7279_tmp[4]_lut_out = E1L119 & A1L4 # !E1L119 & (E1_key_7279_tmp[4]);
E1_key_7279_tmp[4] = DFFEAS(E1_key_7279_tmp[4]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1_key_7279_tmp[5] is U7279:inst|FPGA_7279:inst3|key_7279_tmp[5]
--operation mode is normal

E1_key_7279_tmp[5]_lut_out = E1L120 & A1L4 # !E1L120 & (E1_key_7279_tmp[5]);
E1_key_7279_tmp[5] = DFFEAS(E1_key_7279_tmp[5]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1_key_7279_tmp[7] is U7279:inst|FPGA_7279:inst3|key_7279_tmp[7]
--operation mode is normal

E1_key_7279_tmp[7]_lut_out = E1L121 & A1L4 # !E1L121 & (E1_key_7279_tmp[7]);
E1_key_7279_tmp[7] = DFFEAS(E1_key_7279_tmp[7]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1_key_7279_tmp[6] is U7279:inst|FPGA_7279:inst3|key_7279_tmp[6]
--operation mode is normal

E1_key_7279_tmp[6]_lut_out = E1L122 & A1L4 # !E1L122 & (E1_key_7279_tmp[6]);
E1_key_7279_tmp[6] = DFFEAS(E1_key_7279_tmp[6]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1L114 is U7279:inst|FPGA_7279:inst3|Decoder~220
--operation mode is normal

E1L114 = SYS_RST_N & E1_state.shift_key_high;


--E1L115 is U7279:inst|FPGA_7279:inst3|Decoder~221
--operation mode is normal

E1L115 = !E1_sdata_cnt[0] & !E1_sdata_cnt[1] & !E1_sdata_cnt[2] & E1L114;


--E1L116 is U7279:inst|FPGA_7279:inst3|Decoder~222
--operation mode is normal

E1L116 = E1_sdata_cnt[0] & !E1_sdata_cnt[1] & !E1_sdata_cnt[2] & E1L114;


--E1L117 is U7279:inst|FPGA_7279:inst3|Decoder~223
--operation mode is normal

E1L117 = !E1_sdata_cnt[0] & E1_sdata_cnt[1] & !E1_sdata_cnt[2] & E1L114;


--E1L118 is U7279:inst|FPGA_7279:inst3|Decoder~224
--operation mode is normal

E1L118 = E1_sdata_cnt[0] & E1_sdata_cnt[1] & !E1_sdata_cnt[2] & E1L114;


--E1L119 is U7279:inst|FPGA_7279:inst3|Decoder~225
--operation mode is normal

E1L119 = !E1_sdata_cnt[0] & !E1_sdata_cnt[1] & E1_sdata_cnt[2] & E1L114;


--E1L120 is U7279:inst|FPGA_7279:inst3|Decoder~226
--operation mode is normal

E1L120 = E1_sdata_cnt[0] & !E1_sdata_cnt[1] & E1_sdata_cnt[2] & E1L114;


--E1L121 is U7279:inst|FPGA_7279:inst3|Decoder~227
--operation mode is normal

E1L121 = E1_sdata_cnt[0] & E1_sdata_cnt[1] & E1_sdata_cnt[2] & E1L114;


--E1L122 is U7279:inst|FPGA_7279:inst3|Decoder~228
--operation mode is normal

E1L122 = !E1_sdata_cnt[0] & E1_sdata_cnt[1] & E1_sdata_cnt[2] & E1L114;


--E1L99 is U7279:inst|FPGA_7279:inst3|decode_bus~1191
--operation mode is normal

E1L99 = F1_D_BUS[1] & !F1_D_BUS[3] & (F1_D_BUS[0] # !F1_D_BUS[2]) # !F1_D_BUS[1] & (F1_D_BUS[0] $ !F1_D_BUS[3] # !F1_D_BUS[2]);


--E1L100 is U7279:inst|FPGA_7279:inst3|decode_bus~1192
--operation mode is normal

E1L100 = F1_D_BUS[0] & (!F1_D_BUS[3] # !F1_D_BUS[1]) # !F1_D_BUS[0] & (F1_D_BUS[2] & (!F1_D_BUS[3]) # !F1_D_BUS[2] & !F1_D_BUS[1]);


--E1L101 is U7279:inst|FPGA_7279:inst3|decode_bus~1193
--operation mode is normal

E1L101 = F1_D_BUS[1] & F1_D_BUS[2] & (F1_D_BUS[3] # !F1_D_BUS[0]) # !F1_D_BUS[1] & (F1_D_BUS[2] $ F1_D_BUS[3] # !F1_D_BUS[0]);


--E1L102 is U7279:inst|FPGA_7279:inst3|decode_bus~1194
--operation mode is normal

E1L102 = F1_D_BUS[1] & (F1_D_BUS[2] # !F1_D_BUS[3]) # !F1_D_BUS[1] & (F1_D_BUS[0] & (F1_D_BUS[2] $ F1_D_BUS[3]) # !F1_D_BUS[0] & (F1_D_BUS[3] # !F1_D_BUS[2]));


--E1L103 is U7279:inst|FPGA_7279:inst3|decode_bus~1195
--operation mode is normal

E1L103 = F1_D_BUS[1] & (F1_D_BUS[3] & (F1_D_BUS[2]) # !F1_D_BUS[3] & !F1_D_BUS[0]) # !F1_D_BUS[1] & (F1_D_BUS[2] & (F1_D_BUS[3]) # !F1_D_BUS[2] & !F1_D_BUS[0]);


--E1L104 is U7279:inst|FPGA_7279:inst3|decode_bus~1196
--operation mode is normal

E1L104 = F1_D_BUS[1] & (F1_D_BUS[2] $ !F1_D_BUS[3] # !F1_D_BUS[0]) # !F1_D_BUS[1] & (F1_D_BUS[2] & (F1_D_BUS[0] # !F1_D_BUS[3]) # !F1_D_BUS[2] & (F1_D_BUS[3]));


--SYS_RST_N is SYS_RST_N
--operation mode is input

SYS_RST_N = INPUT();


--SYS_CLK is SYS_CLK
--operation mode is input

SYS_CLK = INPUT();


--KEY7279 is KEY7279
--operation mode is input

KEY7279 = INPUT();


--CS7279 is CS7279
--operation mode is output

CS7279 = OUTPUT(!E1_CS7279);


--CLK7279 is CLK7279
--operation mode is output

CLK7279 = OUTPUT(E1_CLK7279);


--A1L4 is DAT7279~0
--operation mode is bidir

A1L4 = DAT7279;

--DAT7279 is DAT7279
--operation mode is bidir

DAT7279_tri_out = TRI(E1L14Q, E1L181Q);
DAT7279 = BIDIR(DAT7279_tri_out);