top_7279.map.eqn

AD0820小程序

E1_data_7279[0][6] = DFFEAS(E1_data_7279[0][6]_lut_out, !SYS_CLK, SYS_RST_N, , E1L112, , , , );


--E1L162 is U7279:inst|FPGA_7279:inst3|Mux~364
--operation mode is normal

E1L162 = E1_seg_cnt[1] & (E1_seg_cnt[2]) # !E1_seg_cnt[1] & (E1_seg_cnt[2] & E1_data_7279[4][6] # !E1_seg_cnt[2] & (E1_data_7279[0][6]));


--E1_data_7279[6][6] is U7279:inst|FPGA_7279:inst3|data_7279[6][6]
--operation mode is normal

E1_data_7279[6][6]_lut_out = E1L102;
E1_data_7279[6][6] = DFFEAS(E1_data_7279[6][6]_lut_out, !SYS_CLK, SYS_RST_N, , E1L113, , , , );


--E1L163 is U7279:inst|FPGA_7279:inst3|Mux~365
--operation mode is normal

E1L163 = E1_seg_cnt[1] & (E1L162 & (E1_data_7279[6][6]) # !E1L162 & E1_data_7279[2][6]) # !E1_seg_cnt[1] & (E1L162);


--E1_data_7279[5][2] is U7279:inst|FPGA_7279:inst3|data_7279[5][2]
--operation mode is normal

E1_data_7279[5][2]_lut_out = E1L103;
E1_data_7279[5][2] = DFFEAS(E1_data_7279[5][2]_lut_out, !SYS_CLK, SYS_RST_N, , E1L106, , , , );


--E1_data_7279[3][2] is U7279:inst|FPGA_7279:inst3|data_7279[3][2]
--operation mode is normal

E1_data_7279[3][2]_lut_out = E1L103;
E1_data_7279[3][2] = DFFEAS(E1_data_7279[3][2]_lut_out, !SYS_CLK, SYS_RST_N, , E1L107, , , , );


--E1_data_7279[1][2] is U7279:inst|FPGA_7279:inst3|data_7279[1][2]
--operation mode is normal

E1_data_7279[1][2]_lut_out = E1L103;
E1_data_7279[1][2] = DFFEAS(E1_data_7279[1][2]_lut_out, !SYS_CLK, SYS_RST_N, , E1L108, , , , );


--E1L164 is U7279:inst|FPGA_7279:inst3|Mux~367
--operation mode is normal

E1L164 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & E1_data_7279[3][2] # !E1_seg_cnt[1] & (E1_data_7279[1][2]));


--E1_data_7279[7][2] is U7279:inst|FPGA_7279:inst3|data_7279[7][2]
--operation mode is normal

E1_data_7279[7][2]_lut_out = E1L103;
E1_data_7279[7][2] = DFFEAS(E1_data_7279[7][2]_lut_out, !SYS_CLK, SYS_RST_N, , E1L109, , , , );


--E1L165 is U7279:inst|FPGA_7279:inst3|Mux~368
--operation mode is normal

E1L165 = E1_seg_cnt[2] & (E1L164 & (E1_data_7279[7][2]) # !E1L164 & E1_data_7279[5][2]) # !E1_seg_cnt[2] & (E1L164);


--E1_data_7279[2][2] is U7279:inst|FPGA_7279:inst3|data_7279[2][2]
--operation mode is normal

E1_data_7279[2][2]_lut_out = E1L103;
E1_data_7279[2][2] = DFFEAS(E1_data_7279[2][2]_lut_out, !SYS_CLK, SYS_RST_N, , E1L110, , , , );


--E1_data_7279[4][2] is U7279:inst|FPGA_7279:inst3|data_7279[4][2]
--operation mode is normal

E1_data_7279[4][2]_lut_out = E1L103;
E1_data_7279[4][2] = DFFEAS(E1_data_7279[4][2]_lut_out, !SYS_CLK, SYS_RST_N, , E1L111, , , , );


--E1_data_7279[0][2] is U7279:inst|FPGA_7279:inst3|data_7279[0][2]
--operation mode is normal

E1_data_7279[0][2]_lut_out = E1L103;
E1_data_7279[0][2] = DFFEAS(E1_data_7279[0][2]_lut_out, !SYS_CLK, SYS_RST_N, , E1L112, , , , );


--E1L166 is U7279:inst|FPGA_7279:inst3|Mux~369
--operation mode is normal

E1L166 = E1_seg_cnt[1] & (E1_seg_cnt[2]) # !E1_seg_cnt[1] & (E1_seg_cnt[2] & E1_data_7279[4][2] # !E1_seg_cnt[2] & (E1_data_7279[0][2]));


--E1_data_7279[6][2] is U7279:inst|FPGA_7279:inst3|data_7279[6][2]
--operation mode is normal

E1_data_7279[6][2]_lut_out = E1L103;
E1_data_7279[6][2] = DFFEAS(E1_data_7279[6][2]_lut_out, !SYS_CLK, SYS_RST_N, , E1L113, , , , );


--E1L167 is U7279:inst|FPGA_7279:inst3|Mux~370
--operation mode is normal

E1L167 = E1_seg_cnt[1] & (E1L166 & (E1_data_7279[6][2]) # !E1L166 & E1_data_7279[2][2]) # !E1_seg_cnt[1] & (E1L166);


--E1_data_7279[5][1] is U7279:inst|FPGA_7279:inst3|data_7279[5][1]
--operation mode is normal

E1_data_7279[5][1]_lut_out = E1L101;
E1_data_7279[5][1] = DFFEAS(E1_data_7279[5][1]_lut_out, !SYS_CLK, SYS_RST_N, , E1L106, , , , );


--E1_data_7279[3][1] is U7279:inst|FPGA_7279:inst3|data_7279[3][1]
--operation mode is normal

E1_data_7279[3][1]_lut_out = E1L101;
E1_data_7279[3][1] = DFFEAS(E1_data_7279[3][1]_lut_out, !SYS_CLK, SYS_RST_N, , E1L107, , , , );


--E1_data_7279[1][1] is U7279:inst|FPGA_7279:inst3|data_7279[1][1]
--operation mode is normal

E1_data_7279[1][1]_lut_out = E1L101;
E1_data_7279[1][1] = DFFEAS(E1_data_7279[1][1]_lut_out, !SYS_CLK, SYS_RST_N, , E1L108, , , , );


--E1L168 is U7279:inst|FPGA_7279:inst3|Mux~372
--operation mode is normal

E1L168 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & E1_data_7279[3][1] # !E1_seg_cnt[1] & (E1_data_7279[1][1]));


--E1_data_7279[7][1] is U7279:inst|FPGA_7279:inst3|data_7279[7][1]
--operation mode is normal

E1_data_7279[7][1]_lut_out = E1L101;
E1_data_7279[7][1] = DFFEAS(E1_data_7279[7][1]_lut_out, !SYS_CLK, SYS_RST_N, , E1L109, , , , );


--E1L169 is U7279:inst|FPGA_7279:inst3|Mux~373
--operation mode is normal

E1L169 = E1_seg_cnt[2] & (E1L168 & (E1_data_7279[7][1]) # !E1L168 & E1_data_7279[5][1]) # !E1_seg_cnt[2] & (E1L168);


--E1_data_7279[2][1] is U7279:inst|FPGA_7279:inst3|data_7279[2][1]
--operation mode is normal

E1_data_7279[2][1]_lut_out = E1L101;
E1_data_7279[2][1] = DFFEAS(E1_data_7279[2][1]_lut_out, !SYS_CLK, SYS_RST_N, , E1L110, , , , );


--E1_data_7279[4][1] is U7279:inst|FPGA_7279:inst3|data_7279[4][1]
--operation mode is normal

E1_data_7279[4][1]_lut_out = E1L101;
E1_data_7279[4][1] = DFFEAS(E1_data_7279[4][1]_lut_out, !SYS_CLK, SYS_RST_N, , E1L111, , , , );


--E1_data_7279[0][1] is U7279:inst|FPGA_7279:inst3|data_7279[0][1]
--operation mode is normal

E1_data_7279[0][1]_lut_out = E1L101;
E1_data_7279[0][1] = DFFEAS(E1_data_7279[0][1]_lut_out, !SYS_CLK, SYS_RST_N, , E1L112, , , , );


--E1L170 is U7279:inst|FPGA_7279:inst3|Mux~374
--operation mode is normal

E1L170 = E1_seg_cnt[1] & (E1_seg_cnt[2]) # !E1_seg_cnt[1] & (E1_seg_cnt[2] & E1_data_7279[4][1] # !E1_seg_cnt[2] & (E1_data_7279[0][1]));


--E1_data_7279[6][1] is U7279:inst|FPGA_7279:inst3|data_7279[6][1]
--operation mode is normal

E1_data_7279[6][1]_lut_out = E1L101;
E1_data_7279[6][1] = DFFEAS(E1_data_7279[6][1]_lut_out, !SYS_CLK, SYS_RST_N, , E1L113, , , , );


--E1L171 is U7279:inst|FPGA_7279:inst3|Mux~375
--operation mode is normal

E1L171 = E1_seg_cnt[1] & (E1L170 & (E1_data_7279[6][1]) # !E1L170 & E1_data_7279[2][1]) # !E1_seg_cnt[1] & (E1L170);


--E1_data_7279[5][0] is U7279:inst|FPGA_7279:inst3|data_7279[5][0]
--operation mode is normal

E1_data_7279[5][0]_lut_out = E1L104;
E1_data_7279[5][0] = DFFEAS(E1_data_7279[5][0]_lut_out, !SYS_CLK, SYS_RST_N, , E1L106, , , , );


--E1_data_7279[3][0] is U7279:inst|FPGA_7279:inst3|data_7279[3][0]
--operation mode is normal

E1_data_7279[3][0]_lut_out = E1L104;
E1_data_7279[3][0] = DFFEAS(E1_data_7279[3][0]_lut_out, !SYS_CLK, SYS_RST_N, , E1L107, , , , );


--E1_data_7279[1][0] is U7279:inst|FPGA_7279:inst3|data_7279[1][0]
--operation mode is normal

E1_data_7279[1][0]_lut_out = E1L104;
E1_data_7279[1][0] = DFFEAS(E1_data_7279[1][0]_lut_out, !SYS_CLK, SYS_RST_N, , E1L108, , , , );


--E1L172 is U7279:inst|FPGA_7279:inst3|Mux~377
--operation mode is normal

E1L172 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & E1_data_7279[3][0] # !E1_seg_cnt[1] & (E1_data_7279[1][0]));


--E1_data_7279[7][0] is U7279:inst|FPGA_7279:inst3|data_7279[7][0]
--operation mode is normal

E1_data_7279[7][0]_lut_out = E1L104;
E1_data_7279[7][0] = DFFEAS(E1_data_7279[7][0]_lut_out, !SYS_CLK, SYS_RST_N, , E1L109, , , , );


--E1L173 is U7279:inst|FPGA_7279:inst3|Mux~378
--operation mode is normal

E1L173 = E1_seg_cnt[2] & (E1L172 & (E1_data_7279[7][0]) # !E1L172 & E1_data_7279[5][0]) # !E1_seg_cnt[2] & (E1L172);


--E1_data_7279[2][0] is U7279:inst|FPGA_7279:inst3|data_7279[2][0]
--operation mode is normal

E1_data_7279[2][0]_lut_out = E1L104;
E1_data_7279[2][0] = DFFEAS(E1_data_7279[2][0]_lut_out, !SYS_CLK, SYS_RST_N, , E1L110, , , , );


--E1_data_7279[4][0] is U7279:inst|FPGA_7279:inst3|data_7279[4][0]
--operation mode is normal

E1_data_7279[4][0]_lut_out = E1L104;
E1_data_7279[4][0] = DFFEAS(E1_data_7279[4][0]_lut_out, !SYS_CLK, SYS_RST_N, , E1L111, , , , );


--E1_data_7279[0][0] is U7279:inst|FPGA_7279:inst3|data_7279[0][0]
--operation mode is normal

E1_data_7279[0][0]_lut_out = E1L104;
E1_data_7279[0][0] = DFFEAS(E1_data_7279[0][0]_lut_out, !SYS_CLK, SYS_RST_N, , E1L112, , , , );


--E1L174 is U7279:inst|FPGA_7279:inst3|Mux~379
--operation mode is normal

E1L174 = E1_seg_cnt[1] & (E1_seg_cnt[2]) # !E1_seg_cnt[1] & (E1_seg_cnt[2] & E1_data_7279[4][0] # !E1_seg_cnt[2] & (E1_data_7279[0][0]));


--E1_data_7279[6][0] is U7279:inst|FPGA_7279:inst3|data_7279[6][0]
--operation mode is normal

E1_data_7279[6][0]_lut_out = E1L104;
E1_data_7279[6][0] = DFFEAS(E1_data_7279[6][0]_lut_out, !SYS_CLK, SYS_RST_N, , E1L113, , , , );


--E1L175 is U7279:inst|FPGA_7279:inst3|Mux~380
--operation mode is normal

E1L175 = E1_seg_cnt[1] & (E1L174 & (E1_data_7279[6][0]) # !E1L174 & E1_data_7279[2][0]) # !E1_seg_cnt[1] & (E1L174);


--E1_data_7279[5][3] is U7279:inst|FPGA_7279:inst3|data_7279[5][3]
--operation mode is normal

E1_data_7279[5][3]_lut_out = !E1L98;
E1_data_7279[5][3] = DFFEAS(E1_data_7279[5][3]_lut_out, !SYS_CLK, SYS_RST_N, , E1L106, , , , );


--E1_data_7279[3][3] is U7279:inst|FPGA_7279:inst3|data_7279[3][3]
--operation mode is normal

E1_data_7279[3][3]_lut_out = !E1L98;
E1_data_7279[3][3] = DFFEAS(E1_data_7279[3][3]_lut_out, !SYS_CLK, SYS_RST_N, , E1L107, , , , );


--E1_data_7279[1][3] is U7279:inst|FPGA_7279:inst3|data_7279[1][3]
--operation mode is normal

E1_data_7279[1][3]_lut_out = !E1L98;
E1_data_7279[1][3] = DFFEAS(E1_data_7279[1][3]_lut_out, !SYS_CLK, SYS_RST_N, , E1L108, , , , );


--E1L176 is U7279:inst|FPGA_7279:inst3|Mux~382
--operation mode is normal

E1L176 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & E1_data_7279[3][3] # !E1_seg_cnt[1] & (E1_data_7279[1][3]));


--E1_data_7279[7][3] is U7279:inst|FPGA_7279:inst3|data_7279[7][3]
--operation mode is normal

E1_data_7279[7][3]_lut_out = !E1L98;
E1_data_7279[7][3] = DFFEAS(E1_data_7279[7][3]_lut_out, !SYS_CLK, SYS_RST_N, , E1L109, , , , );


--E1L177 is U7279:inst|FPGA_7279:inst3|Mux~383
--operation mode is normal

E1L177 = E1_seg_cnt[2] & (E1L176 & (E1_data_7279[7][3]) # !E1L176 & E1_data_7279[5][3]) # !E1_seg_cnt[2] & (E1L176);


--E1_data_7279[2][3] is U7279:inst|FPGA_7279:inst3|data_7279[2][3]
--operation mode is normal

E1_data_7279[2][3]_lut_out = !E1L98;
E1_data_7279[2][3] = DFFEAS(E1_data_7279[2][3]_lut_out, !SYS_CLK, SYS_RST_N, , E1L110, , , , );


--E1_data_7279[4][3] is U7279:inst|FPGA_7279:inst3|data_7279[4][3]
--operation mode is normal

E1_data_7279[4][3]_lut_out = !E1L98;
E1_data_7279[4][3] = DFFEAS(E1_data_7279[4][3]_lut_out, !SYS_CLK, SYS_RST_N, , E1L111, , , , );


--E1_data_7279[0][3] is U7279:inst|FPGA_7279:inst3|data_7279[0][3]
--operation mode is normal

E1_data_7279[0][3]_lut_out = !E1L98;
E1_data_7279[0][3] = DFFEAS(E1_data_7279[0][3]_lut_out, !SYS_CLK, SYS_RST_N, , E1L112, , , , );


--E1L178 is U7279:inst|FPGA_7279:inst3|Mux~384
--operation mode is normal

E1L178 = E1_seg_cnt[1] & (E1_seg_cnt[2]) # !E1_seg_cnt[1] & (E1_seg_cnt[2] & E1_data_7279[4][3] # !E1_seg_cnt[2] & (E1_data_7279[0][3]));


--E1_data_7279[6][3] is U7279:inst|FPGA_7279:inst3|data_7279[6][3]
--operation mode is normal

E1_data_7279[6][3]_lut_out = !E1L98;
E1_data_7279[6][3] = DFFEAS(E1_data_7279[6][3]_lut_out, !SYS_CLK, SYS_RST_N, , E1L113, , , , );


--E1L179 is U7279:inst|FPGA_7279:inst3|Mux~385
--operation mode is normal

E1L179 = E1_seg_cnt[1] & (E1L178 & (E1_data_7279[6][3]) # !E1L178 & E1_data_7279[2][3]) # !E1_seg_cnt[1] & (E1L178);


--F1_D_BUS[0] is U7279:inst|Display8:inst5|D_BUS[0]
--operation mode is normal

F1_D_BUS[0]_lut_out = C1_Q[28] & (F1_CNT8[1] & F1_CNT8[0] # !F1_CNT8[1] & (F1_CNT8[2])) # !C1_Q[28] & F1_CNT8[0] & (F1_CNT8[2] $ F1_CNT8[1]);
F1_D_BUS[0] = DFFEAS(F1_D_BUS[0]_lut_out, D3_clk_tmp, SYS_RST_N, , F1_state.start, , , , );


--F1_D_BUS[1] is U7279:inst|Display8:inst5|D_BUS[1]
--operation mode is normal

F1_D_BUS[1]_lut_out = F1_CNT8[0] & F1_CNT8[1] # !F1_CNT8[0] & !F1_CNT8[1] & F1_CNT8[2];
F1_D_BUS[1] = DFFEAS(F1_D_BUS[1]_lut_out, D3_clk_tmp, SYS_RST_N, , F1_state.start, , , , );


--F1_D_BUS[2] is U7279:inst|Display8:inst5|D_BUS[2]
--operation mode is normal

F1_D_BUS[2]_lut_out = !F1_CNT8[0] & !F1_CNT8[2] & (F1_CNT8[1] # C1_Q[2]);
F1_D_BUS[2] = DFFEAS(F1_D_BUS[2]_lut_out, D3_clk_tmp, SYS_RST_N, , F1_state.start, , , , );


--F1_D_BUS[3] is U7279:inst|Display8:inst5|D_BUS[3]
--operation mode is normal

F1_D_BUS[3]_lut_out = F1_CNT8[0] & (F1_CNT8[2] $ !F1_CNT8[1]) # !F1_CNT8[0] & F1_CNT8[2] & !F1_CNT8[1] & C1_Q[28];
F1_D_BUS[3] = DFFEAS(F1_D_BUS[3]_lut_out, D3_clk_tmp, SYS_RST_N, , F1_state.start, , , , );


--F1_A_BUS[0] is U7279:inst|Display8:inst5|A_BUS[0]
--operation mode is normal

F1_A_BUS[0]_lut_out = F1_CNT8[0];
F1_A_BUS[0] = DFFEAS(F1_A_BUS[0]_lut_out, D3_clk_tmp, VCC, , F1L3, , , , );


--F1_A_BUS[1] is U7279:inst|Display8:inst5|A_BUS[1]
--operation mode is normal

F1_A_BUS[1]_lut_out = F1_CNT8[1];
F1_A_BUS[1] = DFFEAS(F1_A_BUS[1]_lut_out, D3_clk_tmp, VCC, , F1L3, , , , );


--F1_A_BUS[2] is U7279:inst|Display8:inst5|A_BUS[2]
--operation mode is normal

F1_A_BUS[2]_lut_out = F1_CNT8[2];
F1_A_BUS[2] = DFFEAS(F1_A_BUS[2]_lut_out, D3_clk_tmp, VCC, , F1L3, , , , );


--F1_WR_N is U7279:inst|Display8:inst5|WR_N
--operation mode is normal

F1_WR_N_lut_out = !F1_state.d_hold & F1_state.idle & (F1_WR_N # F1_state.d_setup);
F1_WR_N = DFFEAS(F1_WR_N_lut_out, D3_clk_tmp, SYS_RST_N, , , , , , );


--E1_state1.start_wr is U7279:inst|FPGA_7279:inst3|state1.start_wr
--operation mode is normal

E1_state1.start_wr_lut_out = F1_WR_N & (E1_state1.start_wr # !E1_state1.idle);
E1_state1.start_wr = DFFEAS(E1_state1.start_wr_lut_out, !SYS_CLK, VCC, , SYS_RST_N, , , , );


--E1L105 is U7279:inst|FPGA_7279:inst3|Decoder~211
--operation mode is normal

E1L105 = F1_WR_N & E1_state1.start_wr;


--E1L106 is U7279:inst|FPGA_7279:inst3|Decoder~212
--operation mode is normal

E1L106 = F1_A_BUS[0] & !F1_A_BUS[1] & F1_A_BUS[2] & E1L105;


--E1L107 is U7279:inst|FPGA_7279:inst3|Decoder~213
--operation mode is normal

E1L107 = F1_A_BUS[0] & F1_A_BUS[1] & !F1_A_BUS[2] & E1L105;


--E1L108 is U7279:inst|FPGA_7279:inst3|Decoder~214
--operation mode is normal

E1L108 = F1_A_BUS[0] & !F1_A_BUS[1] & !F1_A_BUS[2] & E1L105;


--E1L109 is U7279:inst|FPGA_7279:inst3|Decoder~215
--operation mode is normal

E1L109 = F1_A_BUS[0] & F1_A_BUS[1] & F1_A_BUS[2] & E1L105;


--E1L110 is U7279:inst|FPGA_7279:inst3|Decoder~216
--operation mode is normal

E1L110 = !F1_A_BUS[0] & F1_A_BUS[1] & !F1_A_BUS[2] & E1L105;


--E1L111 is U7279:inst|FPGA_7279:inst3|Decoder~217
--operation mode is normal

E1L111 = !F1_A_BUS[0] & !F1_A_BUS[1] & F1_A_BUS[2] & E1L105;


--E1L112 is U7279:inst|FPGA_7279:inst3|Decoder~218
--operation mode is normal

E1L112 = !F1_A_BUS[0] & !F1_A_BUS[1] & !F1_A_BUS[2] & E1L105;


--E1L113 is U7279:inst|FPGA_7279:inst3|Decoder~219
--operation mode is normal

E1L113 = !F1_A_BUS[0] & F1_A_BUS[1] & F1_A_BUS[2] & E1L105;


--E1L98 is U7279:inst|FPGA_7279:inst3|decode_bus~1190
--operation mode is normal

E1L98 = F1_D_BUS[1] & (F1_D_BUS[2] & F1_D_BUS[0] # !F1_D_BUS[2] & (F1_D_BUS[3])) # !F1_D_BUS[1] & !F1_D_BUS[3] & (F1_D_BUS[0] $ F1_D_BUS[2]);