top_7279.map.eqn

AD0820小程序

--operation mode is normal

E1L188 = SYS_RST_N & E1L204;


--E1_data_start is U7279:inst|FPGA_7279:inst3|data_start
--operation mode is normal

E1_data_start_lut_out = E1_state.idle & E1_data_start # !E1_state.idle & (KEY7279);
E1_data_start = DFFEAS(E1_data_start_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1L84 is U7279:inst|FPGA_7279:inst3|data_tmp1[0]~7
--operation mode is normal

E1L84 = E1_state.start & SYS_RST_N;


--E1_delay_cnt[0] is U7279:inst|FPGA_7279:inst3|delay_cnt[0]
--operation mode is normal

E1_delay_cnt[0]_lut_out = E1L128 & (E1_state.start # E1_state.shift_cmd_high # !E1_delay_cnt[0]) # !E1L128 & (E1_delay_cnt[0]);
E1_delay_cnt[0] = DFFEAS(E1_delay_cnt[0]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1L182 is U7279:inst|FPGA_7279:inst3|reduce_or~52
--operation mode is normal

E1L182 = E1_state.start # E1_state.next_delay # E1_state.start_delay # E1_state.shift_cmd_high;


--E1L126 is U7279:inst|FPGA_7279:inst3|delay_cnt[1]~779
--operation mode is normal

E1L126 = SYS_RST_N & E1L182 & !E1L203 & !E1L206;


--E1L127 is U7279:inst|FPGA_7279:inst3|delay_cnt[1]~780
--operation mode is normal

E1L127 = !E1_scmd_cnt[2] & !E1_scmd_cnt[1] & !E1_scmd_cnt[0];


--E1L128 is U7279:inst|FPGA_7279:inst3|delay_cnt[1]~781
--operation mode is normal

E1L128 = E1L126 & (E1L180 & E1L127 # !E1_state.shift_cmd_high);


--E1L183 is U7279:inst|FPGA_7279:inst3|reduce_or~53
--operation mode is normal

E1L183 = !E1_state.start & !E1_state.shift_cmd_high;


--E1_seg_cnt[2] is U7279:inst|FPGA_7279:inst3|seg_cnt[2]
--operation mode is normal

E1_seg_cnt[2]_lut_out = E1_seg_cnt[2] $ (E1_seg_cnt[1] & E1_seg_cnt[0] & E1L198);
E1_seg_cnt[2] = DFFEAS(E1_seg_cnt[2]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1L12 is U7279:inst|FPGA_7279:inst3|cmd_tmp[7]~46
--operation mode is normal

E1L12 = SYS_RST_N & (!E1_state.idle);


--E1_seg_cnt[0] is U7279:inst|FPGA_7279:inst3|seg_cnt[0]
--operation mode is normal

E1_seg_cnt[0]_lut_out = !E1_seg_cnt[0];
E1_seg_cnt[0] = DFFEAS(E1_seg_cnt[0]_lut_out, !D2_clk_tmp, VCC, , E1L198, , , , );


--E1_seg_cnt[1] is U7279:inst|FPGA_7279:inst3|seg_cnt[1]
--operation mode is normal

E1_seg_cnt[1]_lut_out = E1_seg_cnt[1] $ (E1_seg_cnt[0] & E1L198);
E1_seg_cnt[1] = DFFEAS(E1_seg_cnt[1]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1_data_tmp1[5] is U7279:inst|FPGA_7279:inst3|data_tmp1[5]
--operation mode is normal

E1_data_tmp1[5]_lut_out = E1_data_tmp[5];
E1_data_tmp1[5] = DFFEAS(E1_data_tmp1[5]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1_data_tmp1[4] is U7279:inst|FPGA_7279:inst3|data_tmp1[4]
--operation mode is normal

E1_data_tmp1[4]_lut_out = E1_data_tmp[4];
E1_data_tmp1[4] = DFFEAS(E1_data_tmp1[4]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1L208 is U7279:inst|FPGA_7279:inst3|Select~1560
--operation mode is normal

E1L208 = E1_sdata_cnt[0] & E1_data_tmp1[5] # !E1_sdata_cnt[0] & (E1_data_tmp1[4]);


--E1_data_tmp1[6] is U7279:inst|FPGA_7279:inst3|data_tmp1[6]
--operation mode is normal

E1_data_tmp1[6]_lut_out = E1_data_tmp[6];
E1_data_tmp1[6] = DFFEAS(E1_data_tmp1[6]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1L209 is U7279:inst|FPGA_7279:inst3|Select~1561
--operation mode is normal

E1L209 = E1_sdata_cnt[1] & (E1_data_tmp1[6] & !E1_sdata_cnt[0]) # !E1_sdata_cnt[1] & E1L208;


--E1_data_tmp1[2] is U7279:inst|FPGA_7279:inst3|data_tmp1[2]
--operation mode is normal

E1_data_tmp1[2]_lut_out = E1_data_tmp[2];
E1_data_tmp1[2] = DFFEAS(E1_data_tmp1[2]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1_data_tmp1[1] is U7279:inst|FPGA_7279:inst3|data_tmp1[1]
--operation mode is normal

E1_data_tmp1[1]_lut_out = E1_data_tmp[1];
E1_data_tmp1[1] = DFFEAS(E1_data_tmp1[1]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1_data_tmp1[0] is U7279:inst|FPGA_7279:inst3|data_tmp1[0]
--operation mode is normal

E1_data_tmp1[0]_lut_out = E1_data_tmp[0];
E1_data_tmp1[0] = DFFEAS(E1_data_tmp1[0]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1L150 is U7279:inst|FPGA_7279:inst3|Mux~350
--operation mode is normal

E1L150 = E1_sdata_cnt[1] & (E1_sdata_cnt[0]) # !E1_sdata_cnt[1] & (E1_sdata_cnt[0] & E1_data_tmp1[1] # !E1_sdata_cnt[0] & (E1_data_tmp1[0]));


--E1_data_tmp1[3] is U7279:inst|FPGA_7279:inst3|data_tmp1[3]
--operation mode is normal

E1_data_tmp1[3]_lut_out = E1_data_tmp[3];
E1_data_tmp1[3] = DFFEAS(E1_data_tmp1[3]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1L151 is U7279:inst|FPGA_7279:inst3|Mux~351
--operation mode is normal

E1L151 = E1_sdata_cnt[1] & (E1L150 & (E1_data_tmp1[3]) # !E1L150 & E1_data_tmp1[2]) # !E1_sdata_cnt[1] & (E1L150);


--E1L210 is U7279:inst|FPGA_7279:inst3|Select~1562
--operation mode is normal

E1L210 = E1_state.shift_data_low & (E1_sdata_cnt[2] & E1L209 # !E1_sdata_cnt[2] & (E1L151));


--E1L211 is U7279:inst|FPGA_7279:inst3|Select~1563
--operation mode is normal

E1L211 = E1_scmd_cnt[2] & (E1_scmd_cnt[1] & E1_cmd_tmp1[7] & E1_scmd_cnt[0] # !E1_scmd_cnt[1] & (!E1_scmd_cnt[0]));


--E1L212 is U7279:inst|FPGA_7279:inst3|Select~1564
--operation mode is normal

E1L212 = E1_cmd_tmp1[2] & E1_scmd_cnt[1] & !E1_scmd_cnt[2] & !E1_scmd_cnt[0];


--E1L213 is U7279:inst|FPGA_7279:inst3|Select~1565
--operation mode is normal

E1L213 = !E1_scmd_cnt[2] & (E1_scmd_cnt[0] & E1_cmd_tmp1[1] # !E1_scmd_cnt[0] & (E1_cmd_tmp1[0]));


--E1L214 is U7279:inst|FPGA_7279:inst3|Select~1566
--operation mode is normal

E1L214 = E1L211 # E1L212 # E1L213 & !E1_scmd_cnt[1];


--E1L215 is U7279:inst|FPGA_7279:inst3|Select~1568
--operation mode is normal

E1L215 = E1_state.idle & (!E1L199) # !E1_state.idle & !KEY7279;


--E1L198 is U7279:inst|FPGA_7279:inst3|seg_cnt[2]~3
--operation mode is normal

E1L198 = SYS_RST_N & KEY7279 & (!E1_state.idle);


--E1_data_tmp[5] is U7279:inst|FPGA_7279:inst3|data_tmp[5]
--operation mode is normal

E1_data_tmp[5]_lut_out = E1_seg_cnt[0] & E1L153 # !E1_seg_cnt[0] & (E1L155);
E1_data_tmp[5] = DFFEAS(E1_data_tmp[5]_lut_out, !D2_clk_tmp, VCC, , E1L198, , , , );


--E1_data_tmp[4] is U7279:inst|FPGA_7279:inst3|data_tmp[4]
--operation mode is normal

E1_data_tmp[4]_lut_out = E1_seg_cnt[0] & E1L157 # !E1_seg_cnt[0] & (E1L159);
E1_data_tmp[4] = DFFEAS(E1_data_tmp[4]_lut_out, !D2_clk_tmp, VCC, , E1L198, , , , );


--E1_data_tmp[6] is U7279:inst|FPGA_7279:inst3|data_tmp[6]
--operation mode is normal

E1_data_tmp[6]_lut_out = E1_seg_cnt[0] & E1L161 # !E1_seg_cnt[0] & (E1L163);
E1_data_tmp[6] = DFFEAS(E1_data_tmp[6]_lut_out, !D2_clk_tmp, VCC, , E1L198, , , , );


--E1_data_tmp[2] is U7279:inst|FPGA_7279:inst3|data_tmp[2]
--operation mode is normal

E1_data_tmp[2]_lut_out = E1_seg_cnt[0] & E1L165 # !E1_seg_cnt[0] & (E1L167);
E1_data_tmp[2] = DFFEAS(E1_data_tmp[2]_lut_out, !D2_clk_tmp, VCC, , E1L198, , , , );


--E1_data_tmp[1] is U7279:inst|FPGA_7279:inst3|data_tmp[1]
--operation mode is normal

E1_data_tmp[1]_lut_out = E1_seg_cnt[0] & E1L169 # !E1_seg_cnt[0] & (E1L171);
E1_data_tmp[1] = DFFEAS(E1_data_tmp[1]_lut_out, !D2_clk_tmp, VCC, , E1L198, , , , );


--E1_data_tmp[0] is U7279:inst|FPGA_7279:inst3|data_tmp[0]
--operation mode is normal

E1_data_tmp[0]_lut_out = E1_seg_cnt[0] & E1L173 # !E1_seg_cnt[0] & (E1L175);
E1_data_tmp[0] = DFFEAS(E1_data_tmp[0]_lut_out, !D2_clk_tmp, VCC, , E1L198, , , , );


--E1_data_tmp[3] is U7279:inst|FPGA_7279:inst3|data_tmp[3]
--operation mode is normal

E1_data_tmp[3]_lut_out = E1_seg_cnt[0] & E1L177 # !E1_seg_cnt[0] & (E1L179);
E1_data_tmp[3] = DFFEAS(E1_data_tmp[3]_lut_out, !D2_clk_tmp, VCC, , E1L198, , , , );


--E1_data_7279[5][5] is U7279:inst|FPGA_7279:inst3|data_7279[5][5]
--operation mode is normal

E1_data_7279[5][5]_lut_out = E1L99;
E1_data_7279[5][5] = DFFEAS(E1_data_7279[5][5]_lut_out, !SYS_CLK, SYS_RST_N, , E1L106, , , , );


--E1_data_7279[3][5] is U7279:inst|FPGA_7279:inst3|data_7279[3][5]
--operation mode is normal

E1_data_7279[3][5]_lut_out = E1L99;
E1_data_7279[3][5] = DFFEAS(E1_data_7279[3][5]_lut_out, !SYS_CLK, SYS_RST_N, , E1L107, , , , );


--E1_data_7279[1][5] is U7279:inst|FPGA_7279:inst3|data_7279[1][5]
--operation mode is normal

E1_data_7279[1][5]_lut_out = E1L99;
E1_data_7279[1][5] = DFFEAS(E1_data_7279[1][5]_lut_out, !SYS_CLK, SYS_RST_N, , E1L108, , , , );


--E1L152 is U7279:inst|FPGA_7279:inst3|Mux~352
--operation mode is normal

E1L152 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & E1_data_7279[3][5] # !E1_seg_cnt[1] & (E1_data_7279[1][5]));


--E1_data_7279[7][5] is U7279:inst|FPGA_7279:inst3|data_7279[7][5]
--operation mode is normal

E1_data_7279[7][5]_lut_out = E1L99;
E1_data_7279[7][5] = DFFEAS(E1_data_7279[7][5]_lut_out, !SYS_CLK, SYS_RST_N, , E1L109, , , , );


--E1L153 is U7279:inst|FPGA_7279:inst3|Mux~353
--operation mode is normal

E1L153 = E1_seg_cnt[2] & (E1L152 & (E1_data_7279[7][5]) # !E1L152 & E1_data_7279[5][5]) # !E1_seg_cnt[2] & (E1L152);


--E1_data_7279[2][5] is U7279:inst|FPGA_7279:inst3|data_7279[2][5]
--operation mode is normal

E1_data_7279[2][5]_lut_out = E1L99;
E1_data_7279[2][5] = DFFEAS(E1_data_7279[2][5]_lut_out, !SYS_CLK, SYS_RST_N, , E1L110, , , , );


--E1_data_7279[4][5] is U7279:inst|FPGA_7279:inst3|data_7279[4][5]
--operation mode is normal

E1_data_7279[4][5]_lut_out = E1L99;
E1_data_7279[4][5] = DFFEAS(E1_data_7279[4][5]_lut_out, !SYS_CLK, SYS_RST_N, , E1L111, , , , );


--E1_data_7279[0][5] is U7279:inst|FPGA_7279:inst3|data_7279[0][5]
--operation mode is normal

E1_data_7279[0][5]_lut_out = E1L99;
E1_data_7279[0][5] = DFFEAS(E1_data_7279[0][5]_lut_out, !SYS_CLK, SYS_RST_N, , E1L112, , , , );


--E1L154 is U7279:inst|FPGA_7279:inst3|Mux~354
--operation mode is normal

E1L154 = E1_seg_cnt[1] & (E1_seg_cnt[2]) # !E1_seg_cnt[1] & (E1_seg_cnt[2] & E1_data_7279[4][5] # !E1_seg_cnt[2] & (E1_data_7279[0][5]));


--E1_data_7279[6][5] is U7279:inst|FPGA_7279:inst3|data_7279[6][5]
--operation mode is normal

E1_data_7279[6][5]_lut_out = E1L99;
E1_data_7279[6][5] = DFFEAS(E1_data_7279[6][5]_lut_out, !SYS_CLK, SYS_RST_N, , E1L113, , , , );


--E1L155 is U7279:inst|FPGA_7279:inst3|Mux~355
--operation mode is normal

E1L155 = E1_seg_cnt[1] & (E1L154 & (E1_data_7279[6][5]) # !E1L154 & E1_data_7279[2][5]) # !E1_seg_cnt[1] & (E1L154);


--E1_data_7279[5][4] is U7279:inst|FPGA_7279:inst3|data_7279[5][4]
--operation mode is normal

E1_data_7279[5][4]_lut_out = E1L100;
E1_data_7279[5][4] = DFFEAS(E1_data_7279[5][4]_lut_out, !SYS_CLK, SYS_RST_N, , E1L106, , , , );


--E1_data_7279[3][4] is U7279:inst|FPGA_7279:inst3|data_7279[3][4]
--operation mode is normal

E1_data_7279[3][4]_lut_out = E1L100;
E1_data_7279[3][4] = DFFEAS(E1_data_7279[3][4]_lut_out, !SYS_CLK, SYS_RST_N, , E1L107, , , , );


--E1_data_7279[1][4] is U7279:inst|FPGA_7279:inst3|data_7279[1][4]
--operation mode is normal

E1_data_7279[1][4]_lut_out = E1L100;
E1_data_7279[1][4] = DFFEAS(E1_data_7279[1][4]_lut_out, !SYS_CLK, SYS_RST_N, , E1L108, , , , );


--E1L156 is U7279:inst|FPGA_7279:inst3|Mux~357
--operation mode is normal

E1L156 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & E1_data_7279[3][4] # !E1_seg_cnt[1] & (E1_data_7279[1][4]));


--E1_data_7279[7][4] is U7279:inst|FPGA_7279:inst3|data_7279[7][4]
--operation mode is normal

E1_data_7279[7][4]_lut_out = E1L100;
E1_data_7279[7][4] = DFFEAS(E1_data_7279[7][4]_lut_out, !SYS_CLK, SYS_RST_N, , E1L109, , , , );


--E1L157 is U7279:inst|FPGA_7279:inst3|Mux~358
--operation mode is normal

E1L157 = E1_seg_cnt[2] & (E1L156 & (E1_data_7279[7][4]) # !E1L156 & E1_data_7279[5][4]) # !E1_seg_cnt[2] & (E1L156);


--E1_data_7279[2][4] is U7279:inst|FPGA_7279:inst3|data_7279[2][4]
--operation mode is normal

E1_data_7279[2][4]_lut_out = E1L100;
E1_data_7279[2][4] = DFFEAS(E1_data_7279[2][4]_lut_out, !SYS_CLK, SYS_RST_N, , E1L110, , , , );


--E1_data_7279[4][4] is U7279:inst|FPGA_7279:inst3|data_7279[4][4]
--operation mode is normal

E1_data_7279[4][4]_lut_out = E1L100;
E1_data_7279[4][4] = DFFEAS(E1_data_7279[4][4]_lut_out, !SYS_CLK, SYS_RST_N, , E1L111, , , , );


--E1_data_7279[0][4] is U7279:inst|FPGA_7279:inst3|data_7279[0][4]
--operation mode is normal

E1_data_7279[0][4]_lut_out = E1L100;
E1_data_7279[0][4] = DFFEAS(E1_data_7279[0][4]_lut_out, !SYS_CLK, SYS_RST_N, , E1L112, , , , );


--E1L158 is U7279:inst|FPGA_7279:inst3|Mux~359
--operation mode is normal

E1L158 = E1_seg_cnt[1] & (E1_seg_cnt[2]) # !E1_seg_cnt[1] & (E1_seg_cnt[2] & E1_data_7279[4][4] # !E1_seg_cnt[2] & (E1_data_7279[0][4]));


--E1_data_7279[6][4] is U7279:inst|FPGA_7279:inst3|data_7279[6][4]
--operation mode is normal

E1_data_7279[6][4]_lut_out = E1L100;
E1_data_7279[6][4] = DFFEAS(E1_data_7279[6][4]_lut_out, !SYS_CLK, SYS_RST_N, , E1L113, , , , );


--E1L159 is U7279:inst|FPGA_7279:inst3|Mux~360
--operation mode is normal

E1L159 = E1_seg_cnt[1] & (E1L158 & (E1_data_7279[6][4]) # !E1L158 & E1_data_7279[2][4]) # !E1_seg_cnt[1] & (E1L158);


--E1_data_7279[5][6] is U7279:inst|FPGA_7279:inst3|data_7279[5][6]
--operation mode is normal

E1_data_7279[5][6]_lut_out = E1L102;
E1_data_7279[5][6] = DFFEAS(E1_data_7279[5][6]_lut_out, !SYS_CLK, SYS_RST_N, , E1L106, , , , );


--E1_data_7279[3][6] is U7279:inst|FPGA_7279:inst3|data_7279[3][6]
--operation mode is normal

E1_data_7279[3][6]_lut_out = E1L102;
E1_data_7279[3][6] = DFFEAS(E1_data_7279[3][6]_lut_out, !SYS_CLK, SYS_RST_N, , E1L107, , , , );


--E1_data_7279[1][6] is U7279:inst|FPGA_7279:inst3|data_7279[1][6]
--operation mode is normal

E1_data_7279[1][6]_lut_out = E1L102;
E1_data_7279[1][6] = DFFEAS(E1_data_7279[1][6]_lut_out, !SYS_CLK, SYS_RST_N, , E1L108, , , , );


--E1L160 is U7279:inst|FPGA_7279:inst3|Mux~362
--operation mode is normal

E1L160 = E1_seg_cnt[2] & (E1_seg_cnt[1]) # !E1_seg_cnt[2] & (E1_seg_cnt[1] & E1_data_7279[3][6] # !E1_seg_cnt[1] & (E1_data_7279[1][6]));


--E1_data_7279[7][6] is U7279:inst|FPGA_7279:inst3|data_7279[7][6]
--operation mode is normal

E1_data_7279[7][6]_lut_out = E1L102;
E1_data_7279[7][6] = DFFEAS(E1_data_7279[7][6]_lut_out, !SYS_CLK, SYS_RST_N, , E1L109, , , , );


--E1L161 is U7279:inst|FPGA_7279:inst3|Mux~363
--operation mode is normal

E1L161 = E1_seg_cnt[2] & (E1L160 & (E1_data_7279[7][6]) # !E1L160 & E1_data_7279[5][6]) # !E1_seg_cnt[2] & (E1L160);


--E1_data_7279[2][6] is U7279:inst|FPGA_7279:inst3|data_7279[2][6]
--operation mode is normal

E1_data_7279[2][6]_lut_out = E1L102;
E1_data_7279[2][6] = DFFEAS(E1_data_7279[2][6]_lut_out, !SYS_CLK, SYS_RST_N, , E1L110, , , , );


--E1_data_7279[4][6] is U7279:inst|FPGA_7279:inst3|data_7279[4][6]
--operation mode is normal

E1_data_7279[4][6]_lut_out = E1L102;
E1_data_7279[4][6] = DFFEAS(E1_data_7279[4][6]_lut_out, !SYS_CLK, SYS_RST_N, , E1L111, , , , );


--E1_data_7279[0][6] is U7279:inst|FPGA_7279:inst3|data_7279[0][6]
--operation mode is normal

E1_data_7279[0][6]_lut_out = E1L102;