top_7279.map.eqn

AD0820小程序

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--E1_CS7279 is U7279:inst|FPGA_7279:inst3|CS7279
--operation mode is normal

E1_CS7279_lut_out = !E1_state.finish & (E1_CS7279 # E1_state.start);
E1_CS7279 = DFFEAS(E1_CS7279_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_CLK7279 is U7279:inst|FPGA_7279:inst3|CLK7279
--operation mode is normal

E1_CLK7279_lut_out = E1_CLK7279 & (E1_state.shift_key_high # !E1L200) # !E1L199;
E1_CLK7279 = DFFEAS(E1_CLK7279_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_state.finish is U7279:inst|FPGA_7279:inst3|state.finish
--operation mode is normal

E1_state.finish_lut_out = E1L201 # E1L202 & (!E1L180);
E1_state.finish = DFFEAS(E1_state.finish_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_state.start is U7279:inst|FPGA_7279:inst3|state.start
--operation mode is normal

E1_state.start_lut_out = !E1_state.idle;
E1_state.start = DFFEAS(E1_state.start_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--D2_clk_tmp is U7279:inst|div:inst1|clk_tmp
--operation mode is normal

D2_clk_tmp_lut_out = D2_clk_tmp $ (D2L22 & (SYS_RST_N));
D2_clk_tmp = DFFEAS(D2_clk_tmp_lut_out, !SYS_CLK, VCC, , , , , , );


--E1_state.shift_key_high is U7279:inst|FPGA_7279:inst3|state.shift_key_high
--operation mode is normal

E1_state.shift_key_high_lut_out = E1_state.shift_key_low;
E1_state.shift_key_high = DFFEAS(E1_state.shift_key_high_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_state.shift_cmd_low is U7279:inst|FPGA_7279:inst3|state.shift_cmd_low
--operation mode is normal

E1_state.shift_cmd_low_lut_out = E1L204;
E1_state.shift_cmd_low = DFFEAS(E1_state.shift_cmd_low_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_state.shift_data_low is U7279:inst|FPGA_7279:inst3|state.shift_data_low
--operation mode is normal

E1_state.shift_data_low_lut_out = E1L205 # E1_state.next_delay & !E1_delay_cnt[1] & !A1L7;
E1_state.shift_data_low = DFFEAS(E1_state.shift_data_low_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_state.shift_key_low is U7279:inst|FPGA_7279:inst3|state.shift_key_low
--operation mode is normal

E1_state.shift_key_low_lut_out = E1L207 # E1_state.next_delay & !E1_delay_cnt[1] & A1L7;
E1_state.shift_key_low = DFFEAS(E1_state.shift_key_low_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1L199 is U7279:inst|FPGA_7279:inst3|Select~1543
--operation mode is normal

E1L199 = !E1_state.shift_cmd_low & !E1_state.shift_data_low & !E1_state.shift_key_low;


--E1_state.next_delay is U7279:inst|FPGA_7279:inst3|state.next_delay
--operation mode is normal

E1_state.next_delay_lut_out = E1_state.next_delay & (E1_delay_cnt[1] # E1L180 & E1L202) # !E1_state.next_delay & E1L180 & E1L202;
E1_state.next_delay = DFFEAS(E1_state.next_delay_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_state.start_delay is U7279:inst|FPGA_7279:inst3|state.start_delay
--operation mode is normal

E1_state.start_delay_lut_out = E1_state.start # E1_state.start_delay & E1_delay_cnt[1];
E1_state.start_delay = DFFEAS(E1_state.start_delay_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_state.idle is U7279:inst|FPGA_7279:inst3|state.idle
--operation mode is normal

E1_state.idle_lut_out = !E1_state.finish;
E1_state.idle = DFFEAS(E1_state.idle_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1L200 is U7279:inst|FPGA_7279:inst3|Select~1544
--operation mode is normal

E1L200 = !E1_state.next_delay & !E1_state.start_delay & !E1_state.finish & E1_state.idle;


--E1_state.shift_key_high1 is U7279:inst|FPGA_7279:inst3|state.shift_key_high1
--operation mode is normal

E1_state.shift_key_high1_lut_out = E1_state.shift_key_high;
E1_state.shift_key_high1 = DFFEAS(E1_state.shift_key_high1_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_state.shift_data_high is U7279:inst|FPGA_7279:inst3|state.shift_data_high
--operation mode is normal

E1_state.shift_data_high_lut_out = E1_state.shift_data_low;
E1_state.shift_data_high = DFFEAS(E1_state.shift_data_high_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_sdata_cnt[2] is U7279:inst|FPGA_7279:inst3|sdata_cnt[2]
--operation mode is normal

E1_sdata_cnt[2]_lut_out = E1L193 & (E1_state.next_delay # E1_sdata_cnt[2] $ !E1L148) # !E1L193 & E1_sdata_cnt[2];
E1_sdata_cnt[2] = DFFEAS(E1_sdata_cnt[2]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1_sdata_cnt[1] is U7279:inst|FPGA_7279:inst3|sdata_cnt[1]
--operation mode is normal

E1_sdata_cnt[1]_lut_out = E1_state.next_delay # E1_sdata_cnt[1] $ !E1_sdata_cnt[0];
E1_sdata_cnt[1] = DFFEAS(E1_sdata_cnt[1]_lut_out, !D2_clk_tmp, VCC, , E1L193, , , , );


--E1_sdata_cnt[0] is U7279:inst|FPGA_7279:inst3|sdata_cnt[0]
--operation mode is normal

E1_sdata_cnt[0]_lut_out = E1_state.next_delay # !E1_sdata_cnt[0];
E1_sdata_cnt[0] = DFFEAS(E1_sdata_cnt[0]_lut_out, !D2_clk_tmp, VCC, , E1L193, , , , );


--E1L148 is U7279:inst|FPGA_7279:inst3|LessThan~111
--operation mode is normal

E1L148 = E1_sdata_cnt[1] # E1_sdata_cnt[0];


--E1L201 is U7279:inst|FPGA_7279:inst3|Select~1546
--operation mode is normal

E1L201 = !E1_sdata_cnt[2] & !E1L148 & (E1_state.shift_key_high1 # E1_state.shift_data_high);


--E1_state.shift_cmd_high is U7279:inst|FPGA_7279:inst3|state.shift_cmd_high
--operation mode is normal

E1_state.shift_cmd_high_lut_out = E1_state.shift_cmd_low;
E1_state.shift_cmd_high = DFFEAS(E1_state.shift_cmd_high_lut_out, !D2_clk_tmp, SYS_RST_N, , , , , , );


--E1_scmd_cnt[2] is U7279:inst|FPGA_7279:inst3|scmd_cnt[2]
--operation mode is normal

E1_scmd_cnt[2]_lut_out = E1L188 & (E1_scmd_cnt[2] $ !E1L149 # !E1_state.shift_cmd_high) # !E1L188 & E1_scmd_cnt[2];
E1_scmd_cnt[2] = DFFEAS(E1_scmd_cnt[2]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1_scmd_cnt[1] is U7279:inst|FPGA_7279:inst3|scmd_cnt[1]
--operation mode is normal

E1_scmd_cnt[1]_lut_out = E1_scmd_cnt[1] $ !E1_scmd_cnt[0] # !E1_state.shift_cmd_high;
E1_scmd_cnt[1] = DFFEAS(E1_scmd_cnt[1]_lut_out, !D2_clk_tmp, VCC, , E1L188, , , , );


--E1_scmd_cnt[0] is U7279:inst|FPGA_7279:inst3|scmd_cnt[0]
--operation mode is normal

E1_scmd_cnt[0]_lut_out = !E1_scmd_cnt[0] # !E1_state.shift_cmd_high;
E1_scmd_cnt[0] = DFFEAS(E1_scmd_cnt[0]_lut_out, !D2_clk_tmp, VCC, , E1L188, , , , );


--E1L202 is U7279:inst|FPGA_7279:inst3|Select~1547
--operation mode is normal

E1L202 = E1_state.shift_cmd_high & !E1_scmd_cnt[2] & !E1_scmd_cnt[1] & !E1_scmd_cnt[0];


--E1_data_start_tmp is U7279:inst|FPGA_7279:inst3|data_start_tmp
--operation mode is normal

E1_data_start_tmp_lut_out = E1_data_start;
E1_data_start_tmp = DFFEAS(E1_data_start_tmp_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1_cmd_tmp1[2] is U7279:inst|FPGA_7279:inst3|cmd_tmp1[2]
--operation mode is normal

E1_cmd_tmp1[2]_lut_out = E1_cmd_tmp[2];
E1_cmd_tmp1[2] = DFFEAS(E1_cmd_tmp1[2]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1_cmd_tmp1[7] is U7279:inst|FPGA_7279:inst3|cmd_tmp1[7]
--operation mode is normal

E1_cmd_tmp1[7]_lut_out = E1_cmd_tmp[7];
E1_cmd_tmp1[7] = DFFEAS(E1_cmd_tmp1[7]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--A1L6 is rtl~188
--operation mode is normal

A1L6 = E1_cmd_tmp1[2] & (!E1_cmd_tmp1[7]);


--E1_cmd_tmp1[0] is U7279:inst|FPGA_7279:inst3|cmd_tmp1[0]
--operation mode is normal

E1_cmd_tmp1[0]_lut_out = E1_cmd_tmp[0];
E1_cmd_tmp1[0] = DFFEAS(E1_cmd_tmp1[0]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1_cmd_tmp1[1] is U7279:inst|FPGA_7279:inst3|cmd_tmp1[1]
--operation mode is normal

E1_cmd_tmp1[1]_lut_out = E1_cmd_tmp[1];
E1_cmd_tmp1[1] = DFFEAS(E1_cmd_tmp1[1]_lut_out, !D2_clk_tmp, VCC, , E1L84, , , , );


--E1L180 is U7279:inst|FPGA_7279:inst3|process0~0
--operation mode is normal

E1L180 = E1_data_start_tmp # A1L6 & E1_cmd_tmp1[0] & !E1_cmd_tmp1[1];


--D2_fre_N[0] is U7279:inst|div:inst1|fre_N[0]
--operation mode is arithmetic

D2_fre_N[0]_lut_out = !D2_fre_N[0];
D2_fre_N[0] = DFFEAS(D2_fre_N[0]_lut_out, !SYS_CLK, SYS_RST_N, , , , , D2L22, );

--D2L4 is U7279:inst|div:inst1|fre_N[0]~144
--operation mode is arithmetic

D2L4 = CARRY(D2_fre_N[0]);


--D2_fre_N[1] is U7279:inst|div:inst1|fre_N[1]
--operation mode is arithmetic

D2_fre_N[1]_carry_eqn = D2L4;
D2_fre_N[1]_lut_out = D2_fre_N[1] $ (D2_fre_N[1]_carry_eqn);
D2_fre_N[1] = DFFEAS(D2_fre_N[1]_lut_out, !SYS_CLK, SYS_RST_N, , , , , D2L22, );

--D2L6 is U7279:inst|div:inst1|fre_N[1]~148
--operation mode is arithmetic

D2L6 = CARRY(!D2L4 # !D2_fre_N[1]);


--D2_fre_N[2] is U7279:inst|div:inst1|fre_N[2]
--operation mode is arithmetic

D2_fre_N[2]_carry_eqn = D2L6;
D2_fre_N[2]_lut_out = D2_fre_N[2] $ (!D2_fre_N[2]_carry_eqn);
D2_fre_N[2] = DFFEAS(D2_fre_N[2]_lut_out, !SYS_CLK, SYS_RST_N, , , , , D2L22, );

--D2L8 is U7279:inst|div:inst1|fre_N[2]~152
--operation mode is arithmetic

D2L8 = CARRY(D2_fre_N[2] & (!D2L6));


--D2_fre_N[3] is U7279:inst|div:inst1|fre_N[3]
--operation mode is arithmetic

D2_fre_N[3]_carry_eqn = D2L8;
D2_fre_N[3]_lut_out = D2_fre_N[3] $ (D2_fre_N[3]_carry_eqn);
D2_fre_N[3] = DFFEAS(D2_fre_N[3]_lut_out, !SYS_CLK, SYS_RST_N, , , , , D2L22, );

--D2L10 is U7279:inst|div:inst1|fre_N[3]~156
--operation mode is arithmetic

D2L10 = CARRY(!D2L8 # !D2_fre_N[3]);


--D2L20 is U7279:inst|div:inst1|LessThan~118
--operation mode is normal

D2L20 = !D2_fre_N[3] # !D2_fre_N[2] # !D2_fre_N[1] # !D2_fre_N[0];


--D2_fre_N[4] is U7279:inst|div:inst1|fre_N[4]
--operation mode is arithmetic

D2_fre_N[4]_carry_eqn = D2L10;
D2_fre_N[4]_lut_out = D2_fre_N[4] $ (!D2_fre_N[4]_carry_eqn);
D2_fre_N[4] = DFFEAS(D2_fre_N[4]_lut_out, !SYS_CLK, SYS_RST_N, , , , , D2L22, );

--D2L12 is U7279:inst|div:inst1|fre_N[4]~160
--operation mode is arithmetic

D2L12 = CARRY(D2_fre_N[4] & (!D2L10));


--D2_fre_N[5] is U7279:inst|div:inst1|fre_N[5]
--operation mode is arithmetic

D2_fre_N[5]_carry_eqn = D2L12;
D2_fre_N[5]_lut_out = D2_fre_N[5] $ (D2_fre_N[5]_carry_eqn);
D2_fre_N[5] = DFFEAS(D2_fre_N[5]_lut_out, !SYS_CLK, SYS_RST_N, , , , , D2L22, );

--D2L14 is U7279:inst|div:inst1|fre_N[5]~164
--operation mode is arithmetic

D2L14 = CARRY(!D2L12 # !D2_fre_N[5]);


--D2_fre_N[6] is U7279:inst|div:inst1|fre_N[6]
--operation mode is arithmetic

D2_fre_N[6]_carry_eqn = D2L14;
D2_fre_N[6]_lut_out = D2_fre_N[6] $ (!D2_fre_N[6]_carry_eqn);
D2_fre_N[6] = DFFEAS(D2_fre_N[6]_lut_out, !SYS_CLK, SYS_RST_N, , , , , D2L22, );

--D2L16 is U7279:inst|div:inst1|fre_N[6]~168
--operation mode is arithmetic

D2L16 = CARRY(D2_fre_N[6] & (!D2L14));


--D2L21 is U7279:inst|div:inst1|LessThan~119
--operation mode is normal

D2L21 = !D2_fre_N[4] & !D2_fre_N[5] & !D2_fre_N[6];


--D2_fre_N[7] is U7279:inst|div:inst1|fre_N[7]
--operation mode is arithmetic

D2_fre_N[7]_carry_eqn = D2L16;
D2_fre_N[7]_lut_out = D2_fre_N[7] $ (D2_fre_N[7]_carry_eqn);
D2_fre_N[7] = DFFEAS(D2_fre_N[7]_lut_out, !SYS_CLK, SYS_RST_N, , , , , D2L22, );

--D2L18 is U7279:inst|div:inst1|fre_N[7]~172
--operation mode is arithmetic

D2L18 = CARRY(!D2L16 # !D2_fre_N[7]);


--D2_fre_N[8] is U7279:inst|div:inst1|fre_N[8]
--operation mode is normal

D2_fre_N[8]_carry_eqn = D2L18;
D2_fre_N[8]_lut_out = D2_fre_N[8] $ (!D2_fre_N[8]_carry_eqn);
D2_fre_N[8] = DFFEAS(D2_fre_N[8]_lut_out, !SYS_CLK, SYS_RST_N, , , , , D2L22, );


--D2L22 is U7279:inst|div:inst1|LessThan~120
--operation mode is normal

D2L22 = D2_fre_N[7] & D2_fre_N[8] & (!D2L21 # !D2L20);


--E1_delay_cnt[1] is U7279:inst|FPGA_7279:inst3|delay_cnt[1]
--operation mode is normal

E1_delay_cnt[1]_lut_out = E1L128 & (E1_delay_cnt[1] $ !E1_delay_cnt[0] # !E1L183) # !E1L128 & E1_delay_cnt[1];
E1_delay_cnt[1] = DFFEAS(E1_delay_cnt[1]_lut_out, !D2_clk_tmp, VCC, , , , , , );


--E1L203 is U7279:inst|FPGA_7279:inst3|Select~1549
--operation mode is normal

E1L203 = E1_state.start_delay & (!E1_delay_cnt[1]);


--E1L149 is U7279:inst|FPGA_7279:inst3|LessThan~112
--operation mode is normal

E1L149 = E1_scmd_cnt[1] # E1_scmd_cnt[0];


--E1L204 is U7279:inst|FPGA_7279:inst3|Select~1550
--operation mode is normal

E1L204 = E1L203 # E1_state.shift_cmd_high & (E1_scmd_cnt[2] # E1L149);


--E1L205 is U7279:inst|FPGA_7279:inst3|Select~1551
--operation mode is normal

E1L205 = E1_state.shift_data_high & (E1_sdata_cnt[2] # E1_sdata_cnt[1] # E1_sdata_cnt[0]);


--E1L206 is U7279:inst|FPGA_7279:inst3|Select~1552
--operation mode is normal

E1L206 = E1_state.next_delay & (!E1_delay_cnt[1]);


--E1_cmd_tmp[2] is U7279:inst|FPGA_7279:inst3|cmd_tmp[2]
--operation mode is normal

E1_cmd_tmp[2]_lut_out = E1_seg_cnt[2] # !KEY7279;
E1_cmd_tmp[2] = DFFEAS(E1_cmd_tmp[2]_lut_out, !D2_clk_tmp, VCC, , E1L12, , , , );


--E1_cmd_tmp[0] is U7279:inst|FPGA_7279:inst3|cmd_tmp[0]
--operation mode is normal

E1_cmd_tmp[0]_lut_out = E1_seg_cnt[0] # !KEY7279;
E1_cmd_tmp[0] = DFFEAS(E1_cmd_tmp[0]_lut_out, !D2_clk_tmp, VCC, , E1L12, , , , );


--E1_cmd_tmp[7] is U7279:inst|FPGA_7279:inst3|cmd_tmp[7]
--operation mode is normal

E1_cmd_tmp[7]_lut_out = KEY7279;
E1_cmd_tmp[7] = DFFEAS(E1_cmd_tmp[7]_lut_out, !D2_clk_tmp, VCC, , E1L12, , , , );


--E1_cmd_tmp[1] is U7279:inst|FPGA_7279:inst3|cmd_tmp[1]
--operation mode is normal

E1_cmd_tmp[1]_lut_out = KEY7279 & E1_seg_cnt[1];
E1_cmd_tmp[1] = DFFEAS(E1_cmd_tmp[1]_lut_out, !D2_clk_tmp, VCC, , E1L12, , , , );


--A1L7 is rtl~189
--operation mode is normal

A1L7 = E1_cmd_tmp[2] & E1_cmd_tmp[0] & !E1_cmd_tmp[7] & !E1_cmd_tmp[1];


--E1L207 is U7279:inst|FPGA_7279:inst3|Select~1553
--operation mode is normal

E1L207 = E1_state.shift_key_high1 & (E1_sdata_cnt[2] # E1_sdata_cnt[1] # E1_sdata_cnt[0]);


--E1L14Q is U7279:inst|FPGA_7279:inst3|DAT7279~reg0
--operation mode is normal

E1L14Q_lut_out = E1L210 # E1L214 & (!E1_state.shift_data_low);
E1L14Q = DFFEAS(E1L14Q_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L215, , , , );


--E1L181Q is U7279:inst|FPGA_7279:inst3|process0~1
--operation mode is normal

E1L181Q_lut_out = !E1_state.shift_key_low & (E1_state.idle);
E1L181Q = DFFEAS(E1L181Q_lut_out, !D2_clk_tmp, SYS_RST_N, , E1L215, , , , );


--E1L193 is U7279:inst|FPGA_7279:inst3|sdata_cnt[2]~426
--operation mode is normal

E1L193 = SYS_RST_N & (E1L205 # E1L206 # E1L207);


--E1L188 is U7279:inst|FPGA_7279:inst3|scmd_cnt[2]~333