📄 top_7279.sim.rpt
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; |top_7279|Test_Controller:inst4|state.wr_stop ; |top_7279|Test_Controller:inst4|state.wr_stop ; regout ;
; |top_7279|Test_Controller:inst4|state.d_setup1 ; |top_7279|Test_Controller:inst4|state.d_setup1 ; regout ;
; |top_7279|FPGA_7279:inst|state1.stop ; |top_7279|FPGA_7279:inst|state1.stop ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~835 ; |top_7279|FPGA_7279:inst|decode_bus~835 ; combout ;
; |top_7279|FPGA_7279:inst|decode_bus~836 ; |top_7279|FPGA_7279:inst|decode_bus~836 ; combout ;
; |top_7279|FPGA_7279:inst|decode_bus~837 ; |top_7279|FPGA_7279:inst|decode_bus~837 ; combout ;
; |top_7279|FPGA_7279:inst|decode_bus~838 ; |top_7279|FPGA_7279:inst|decode_bus~838 ; combout ;
; |top_7279|SYS_CLK ; |top_7279|SYS_CLK ; combout ;
; |top_7279|KEY7279 ; |top_7279|KEY7279 ; combout ;
; |top_7279|CLK20us ; |top_7279|CLK20us ; padio ;
; |top_7279|KEY_EN ; |top_7279|KEY_EN ; padio ;
; |top_7279|CS7279 ; |top_7279|CS7279 ; padio ;
; |top_7279|CLK7279 ; |top_7279|CLK7279 ; padio ;
; |top_7279|OUT7279[7] ; |top_7279|OUT7279[7] ; padio ;
; |top_7279|OUT7279[4] ; |top_7279|OUT7279[4] ; padio ;
; |top_7279|OUT7279[2] ; |top_7279|OUT7279[2] ; padio ;
; |top_7279|DAT7279~0 ; |top_7279|DAT7279~0 ; combout ;
; |top_7279|DAT7279~0 ; |top_7279|DAT7279~output ; padio ;
+------------------------------------------------+------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+------------------------------------------------+------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------------------------------------+------------------------------------------------+------------------+
; |top_7279|div:inst1|fre_N[5] ; |top_7279|div:inst1|fre_N[5]~164 ; cout0 ;
; |top_7279|div:inst1|fre_N[6] ; |top_7279|div:inst1|fre_N[6]~168 ; cout0 ;
; |top_7279|div:inst1|fre_N[7] ; |top_7279|div:inst1|fre_N[7]~172 ; cout0 ;
; |top_7279|FPGA_7279:inst|data_tmp[5] ; |top_7279|FPGA_7279:inst|data_tmp[5] ; regout ;
; |top_7279|FPGA_7279:inst|data_tmp[2] ; |top_7279|FPGA_7279:inst|data_tmp[2] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[1][5] ; |top_7279|FPGA_7279:inst|data_7279[1][5] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[0][5] ; |top_7279|FPGA_7279:inst|data_7279[0][5] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[6][5] ; |top_7279|FPGA_7279:inst|data_7279[6][5] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[1][2] ; |top_7279|FPGA_7279:inst|data_7279[1][2] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[0][2] ; |top_7279|FPGA_7279:inst|data_7279[0][2] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[6][2] ; |top_7279|FPGA_7279:inst|data_7279[6][2] ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~832 ; |top_7279|FPGA_7279:inst|decode_bus~832 ; combout ;
; |top_7279|Test_Controller:inst4|key_7279[5][0] ; |top_7279|Test_Controller:inst4|key_7279[5][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[3][0] ; |top_7279|Test_Controller:inst4|key_7279[3][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[1][0] ; |top_7279|Test_Controller:inst4|key_7279[1][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[7][0] ; |top_7279|Test_Controller:inst4|key_7279[7][0] ; regout ;
; |top_7279|Test_Controller:inst4|Mux~153 ; |top_7279|Test_Controller:inst4|Mux~153 ; combout ;
; |top_7279|Test_Controller:inst4|key_7279[2][0] ; |top_7279|Test_Controller:inst4|key_7279[2][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[4][0] ; |top_7279|Test_Controller:inst4|key_7279[4][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[6][0] ; |top_7279|Test_Controller:inst4|key_7279[6][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[5][2] ; |top_7279|Test_Controller:inst4|key_7279[5][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[3][2] ; |top_7279|Test_Controller:inst4|key_7279[3][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[7][2] ; |top_7279|Test_Controller:inst4|key_7279[7][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[4][2] ; |top_7279|Test_Controller:inst4|key_7279[4][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[6][2] ; |top_7279|Test_Controller:inst4|key_7279[6][2] ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~835 ; |top_7279|FPGA_7279:inst|data_7279[5][5] ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~837 ; |top_7279|FPGA_7279:inst|data_7279[5][2] ; regout ;
; |top_7279|CS_8019 ; |top_7279|CS_8019 ; padio ;
+------------------------------------------------+------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+------------------------------------------------+------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+------------------------------------------------+------------------------------------------------+------------------+
; |top_7279|FPGA_7279:inst|key_7279[6] ; |top_7279|FPGA_7279:inst|key_7279[6] ; regout ;
; |top_7279|FPGA_7279:inst|key_7279[5] ; |top_7279|FPGA_7279:inst|key_7279[5] ; regout ;
; |top_7279|FPGA_7279:inst|key_7279[3] ; |top_7279|FPGA_7279:inst|key_7279[3] ; regout ;
; |top_7279|FPGA_7279:inst|key_7279[1] ; |top_7279|FPGA_7279:inst|key_7279[1] ; regout ;
; |top_7279|FPGA_7279:inst|key_7279[0] ; |top_7279|FPGA_7279:inst|key_7279[0] ; regout ;
; |top_7279|div:inst1|fre_N[5] ; |top_7279|div:inst1|fre_N[5]~164 ; cout0 ;
; |top_7279|div:inst1|fre_N[6] ; |top_7279|div:inst1|fre_N[6]~168 ; cout0 ;
; |top_7279|div:inst1|fre_N[7] ; |top_7279|div:inst1|fre_N[7]~172 ; cout0 ;
; |top_7279|FPGA_7279:inst|key_7279_tmp[3] ; |top_7279|FPGA_7279:inst|key_7279_tmp[3] ; regout ;
; |top_7279|FPGA_7279:inst|data_tmp[5] ; |top_7279|FPGA_7279:inst|data_tmp[5] ; regout ;
; |top_7279|FPGA_7279:inst|data_tmp[2] ; |top_7279|FPGA_7279:inst|data_tmp[2] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[1][5] ; |top_7279|FPGA_7279:inst|data_7279[1][5] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[0][5] ; |top_7279|FPGA_7279:inst|data_7279[0][5] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[6][5] ; |top_7279|FPGA_7279:inst|data_7279[6][5] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[1][4] ; |top_7279|FPGA_7279:inst|data_7279[1][4] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[0][4] ; |top_7279|FPGA_7279:inst|data_7279[0][4] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[6][4] ; |top_7279|FPGA_7279:inst|data_7279[6][4] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[1][6] ; |top_7279|FPGA_7279:inst|data_7279[1][6] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[0][6] ; |top_7279|FPGA_7279:inst|data_7279[0][6] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[6][6] ; |top_7279|FPGA_7279:inst|data_7279[6][6] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[1][2] ; |top_7279|FPGA_7279:inst|data_7279[1][2] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[0][2] ; |top_7279|FPGA_7279:inst|data_7279[0][2] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[6][2] ; |top_7279|FPGA_7279:inst|data_7279[6][2] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[1][1] ; |top_7279|FPGA_7279:inst|data_7279[1][1] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[0][1] ; |top_7279|FPGA_7279:inst|data_7279[0][1] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[6][1] ; |top_7279|FPGA_7279:inst|data_7279[6][1] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[1][0] ; |top_7279|FPGA_7279:inst|data_7279[1][0] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[0][0] ; |top_7279|FPGA_7279:inst|data_7279[0][0] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[6][0] ; |top_7279|FPGA_7279:inst|data_7279[6][0] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[5][3] ; |top_7279|FPGA_7279:inst|data_7279[5][3] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[3][3] ; |top_7279|FPGA_7279:inst|data_7279[3][3] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[1][3] ; |top_7279|FPGA_7279:inst|data_7279[1][3] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[7][3] ; |top_7279|FPGA_7279:inst|data_7279[7][3] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[2][3] ; |top_7279|FPGA_7279:inst|data_7279[2][3] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[4][3] ; |top_7279|FPGA_7279:inst|data_7279[4][3] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[0][3] ; |top_7279|FPGA_7279:inst|data_7279[0][3] ; regout ;
; |top_7279|FPGA_7279:inst|data_7279[6][3] ; |top_7279|FPGA_7279:inst|data_7279[6][3] ; regout ;
; |top_7279|Test_Controller:inst4|D_BUS[0] ; |top_7279|Test_Controller:inst4|D_BUS[0] ; regout ;
; |top_7279|Test_Controller:inst4|D_BUS[3] ; |top_7279|Test_Controller:inst4|D_BUS[3] ; regout ;
; |top_7279|Test_Controller:inst4|D_BUS[1] ; |top_7279|Test_Controller:inst4|D_BUS[1] ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~832 ; |top_7279|FPGA_7279:inst|decode_bus~832 ; combout ;
; |top_7279|FPGA_7279:inst|decode_bus~832 ; |top_7279|FPGA_7279:inst|data_7279[5][4] ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~833 ; |top_7279|FPGA_7279:inst|data_7279[5][1] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[5][0] ; |top_7279|Test_Controller:inst4|key_7279[5][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[3][0] ; |top_7279|Test_Controller:inst4|key_7279[3][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[1][0] ; |top_7279|Test_Controller:inst4|key_7279[1][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[7][0] ; |top_7279|Test_Controller:inst4|key_7279[7][0] ; regout ;
; |top_7279|Test_Controller:inst4|Mux~153 ; |top_7279|Test_Controller:inst4|Mux~153 ; combout ;
; |top_7279|Test_Controller:inst4|key_7279[2][0] ; |top_7279|Test_Controller:inst4|key_7279[2][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[4][0] ; |top_7279|Test_Controller:inst4|key_7279[4][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[6][0] ; |top_7279|Test_Controller:inst4|key_7279[6][0] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[5][2] ; |top_7279|Test_Controller:inst4|key_7279[5][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[3][2] ; |top_7279|Test_Controller:inst4|key_7279[3][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[1][2] ; |top_7279|Test_Controller:inst4|key_7279[1][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[7][2] ; |top_7279|Test_Controller:inst4|key_7279[7][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[2][2] ; |top_7279|Test_Controller:inst4|key_7279[2][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[4][2] ; |top_7279|Test_Controller:inst4|key_7279[4][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[6][2] ; |top_7279|Test_Controller:inst4|key_7279[6][2] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[5][3] ; |top_7279|Test_Controller:inst4|key_7279[5][3] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[3][3] ; |top_7279|Test_Controller:inst4|key_7279[3][3] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[7][3] ; |top_7279|Test_Controller:inst4|key_7279[7][3] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[4][3] ; |top_7279|Test_Controller:inst4|key_7279[4][3] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[0][3] ; |top_7279|Test_Controller:inst4|key_7279[0][3] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[6][3] ; |top_7279|Test_Controller:inst4|key_7279[6][3] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[5][1] ; |top_7279|Test_Controller:inst4|key_7279[5][1] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[3][1] ; |top_7279|Test_Controller:inst4|key_7279[3][1] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[7][1] ; |top_7279|Test_Controller:inst4|key_7279[7][1] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[4][1] ; |top_7279|Test_Controller:inst4|key_7279[4][1] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[0][1] ; |top_7279|Test_Controller:inst4|key_7279[0][1] ; regout ;
; |top_7279|Test_Controller:inst4|key_7279[6][1] ; |top_7279|Test_Controller:inst4|key_7279[6][1] ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~835 ; |top_7279|FPGA_7279:inst|data_7279[5][5] ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~836 ; |top_7279|FPGA_7279:inst|data_7279[5][6] ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~837 ; |top_7279|FPGA_7279:inst|data_7279[5][2] ; regout ;
; |top_7279|FPGA_7279:inst|decode_bus~838 ; |top_7279|FPGA_7279:inst|data_7279[5][0] ; regout ;
; |top_7279|SYS_RST_N ; |top_7279|SYS_RST_N ; combout ;
; |top_7279|CS_8019 ; |top_7279|CS_8019 ; padio ;
; |top_7279|OUT7279[6] ; |top_7279|OUT7279[6] ; padio ;
; |top_7279|OUT7279[5] ; |top_7279|OUT7279[5] ; padio ;
; |top_7279|OUT7279[3] ; |top_7279|OUT7279[3] ; padio ;
; |top_7279|OUT7279[1] ; |top_7279|OUT7279[1] ; padio ;
; |top_7279|OUT7279[0] ; |top_7279|OUT7279[0] ; padio ;
+------------------------------------------------+------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
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