top_7279.tan.summary

AD0820小程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.131 ns
From           : KEY7279
To             : U7279:inst|FPGA_7279:inst3|data_tmp[2]
From Clock     : --
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.074 ns
From           : U7279:inst|FPGA_7279:inst3|process0~1
To             : DAT7279
From Clock     : SYS_CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.790 ns
From           : SYS_RST_N
To             : U7279:inst|FPGA_7279:inst3|scmd_cnt[2]
From Clock     : --
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Clock Setup: 'SYS_CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 50.49 MHz ( period = 19.804 ns )
From           : U7279:inst|Display8:inst5|WR_N
To             : U7279:inst|FPGA_7279:inst3|data_7279[3][5]
From Clock     : SYS_CLK
To Clock       : SYS_CLK
Failed Paths   : 0

Type           : Clock Hold: 'SYS_CLK'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : U7279:inst|FPGA_7279:inst3|data_7279[7][1]
To             : U7279:inst|FPGA_7279:inst3|data_tmp[1]
From Clock     : SYS_CLK
To Clock       : SYS_CLK
Failed Paths   : 52

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 52

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