top_7279.fit.rpt

AD0820小程序

; Perform Physical Synthesis for Combinational Logic   ; Off                            ; Off                            ;
; Perform Register Duplication                         ; Off                            ; Off                            ;
; Perform Register Retiming                            ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining               ; Off                            ; Off                            ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication             ; Auto                           ; Auto                           ;
; Auto Register Duplication                            ; Off                            ; Off                            ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC                          ; Off                 ;
; Reserve ASDO pin after configuration.        ; As input tri-stated ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/vhdl code/HD7279/top_7279.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/vhdl code/HD7279/top_7279.pin.


+-------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                       ;
+---------------------------------------------+---------------------------------------+
; Resource                                    ; Usage                                 ;
+---------------------------------------------+---------------------------------------+
; Total logic elements                        ; 217 / 12,060 ( 2 % )                  ;
;     -- Combinational with no register       ; 49                                    ;
;     -- Register only                        ; 34                                    ;
;     -- Combinational with a register        ; 134                                   ;
;                                             ;                                       ;
; Logic element usage by number of LUT inputs ;                                       ;
;     -- 4 input functions                    ; 94                                    ;
;     -- 3 input functions                    ; 36                                    ;
;     -- 2 input functions                    ; 31                                    ;
;     -- 1 input functions                    ; 27                                    ;
;     -- 0 input functions                    ; 29                                    ;
;                                             ;                                       ;
; Logic elements by mode                      ;                                       ;
;     -- normal mode                          ; 209                                   ;
;     -- arithmetic mode                      ; 8                                     ;
;     -- qfbk mode                            ; 40                                    ;
;     -- register cascade mode                ; 0                                     ;
;     -- synchronous clear/load mode          ; 78                                    ;
;     -- asynchronous clear/load mode         ; 116                                   ;
;                                             ;                                       ;
; Total LABs                                  ; 29 / 1,206 ( 2 % )                    ;
; Logic elements in carry chains              ; 9                                     ;
; User inserted logic elements                ; 0                                     ;
; Virtual pins                                ; 0                                     ;
; I/O pins                                    ; 6 / 173 ( 3 % )                       ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )                        ;
; Global signals                              ; 4                                     ;
; M4Ks                                        ; 0 / 52 ( 0 % )                        ;
; Total memory bits                           ; 0 / 239,616 ( 0 % )                   ;
; Total RAM block bits                        ; 0 / 239,616 ( 0 % )                   ;
; PLLs                                        ; 0 / 2 ( 0 % )                         ;
; Global clocks                               ; 4 / 8 ( 50 % )                        ;
; Maximum fan-out node                        ; SYS_RST_N                             ;
; Maximum fan-out                             ; 128                                   ;
; Highest non-global fan-out signal           ; U7279:inst|FPGA_7279:inst3|seg_cnt[1] ;
; Highest non-global fan-out                  ; 24                                    ;
; Total fan-out                               ; 1001                                  ;
; Average fan-out                             ; 4.45                                  ;
+---------------------------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                      ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name      ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; KEY7279   ; 159   ; 3        ; 53           ; 20           ; 2           ; 8                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
; SYS_CLK   ; 153   ; 3        ; 53           ; 15           ; 1           ; 74                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
; SYS_RST_N ; 131   ; 3        ; 53           ; 4            ; 2           ; 128                   ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
+-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                                      ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load        ;