filter.sim.rpt

图像处理技术中3*3模板的滤波电路的VHDL实现.

; |filter|add8_9:add8_92|s[7]                                                     ; |filter|add8_9:add8_92|s[7]                                                     ; regout           ;
; |filter|add8_9:add8_92|s[6]                                                     ; |filter|add8_9:add8_92|s[6]                                                     ; regout           ;
; |filter|add8_9:add8_92|l1[6]                                                    ; |filter|add8_9:add8_92|l1[6]                                                    ; regout           ;
; |filter|add8_9:add8_92|l1[7]                                                    ; |filter|add8_9:add8_92|l1[7]                                                    ; regout           ;
; |filter|add8_9:add8_91|s[8]                                                     ; |filter|add8_9:add8_91|s[8]                                                     ; regout           ;
; |filter|add8_9:add8_91|s[7]                                                     ; |filter|add8_9:add8_91|s[7]                                                     ; regout           ;
; |filter|add8_9:add8_91|s[0]                                                     ; |filter|add8_9:add8_91|s[0]                                                     ; regout           ;
; |filter|add8_9:add8_91|l2[6]                                                    ; |filter|add8_9:add8_91|l2[6]                                                    ; regout           ;
; |filter|add8_9:add8_91|l2[7]                                                    ; |filter|add8_9:add8_91|l2[7]                                                    ; regout           ;
; |filter|add8_9:add8_91|l1[6]                                                    ; |filter|add8_9:add8_91|l1[6]                                                    ; regout           ;
; |filter|add8_9:add8_91|l1[7]                                                    ; |filter|add8_9:add8_91|l1[7]                                                    ; regout           ;
; |filter|reg8:reg8_23|out_data[7]                                                ; |filter|reg8:reg8_23|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_23|out_data[6]                                                ; |filter|reg8:reg8_23|out_data[6]                                                ; regout           ;
; |filter|reg8:reg8_22|out_data[7]                                                ; |filter|reg8:reg8_22|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_22|out_data[6]                                                ; |filter|reg8:reg8_22|out_data[6]                                                ; regout           ;
; |filter|reg8:reg8_21|out_data[7]                                                ; |filter|reg8:reg8_21|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_21|out_data[6]                                                ; |filter|reg8:reg8_21|out_data[6]                                                ; regout           ;
; |filter|reg8:reg8_13|out_data[7]                                                ; |filter|reg8:reg8_13|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_13|out_data[6]                                                ; |filter|reg8:reg8_13|out_data[6]                                                ; regout           ;
; |filter|reg8:reg8_12|out_data[7]                                                ; |filter|reg8:reg8_12|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_12|out_data[6]                                                ; |filter|reg8:reg8_12|out_data[6]                                                ; regout           ;
; |filter|reg8:reg8_11|out_data[7]                                                ; |filter|reg8:reg8_11|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_11|out_data[6]                                                ; |filter|reg8:reg8_11|out_data[6]                                                ; regout           ;
; |filter|add_1p:add9|lpm_add_sub:add_1|add_sub_qjc:auto_generated|op_1~44        ; |filter|add_1p:add9|lpm_add_sub:add_1|add_sub_qjc:auto_generated|op_1~44        ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_1|add_sub_qjc:auto_generated|op_1~70        ; |filter|add_1p:add9|lpm_add_sub:add_1|add_sub_qjc:auto_generated|op_1~70        ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~45     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~45     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~46     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~46     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~49     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~49     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~51     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~51     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~73     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~73     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~75     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~75     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~77     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~77     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~78     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~78     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~79     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~79     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~80     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~80     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~81     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~81     ; out0             ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
    Info: Processing started: Mon Feb 23 19:25:59 2009
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off filter -c filter
Info: Using vector source file "F:/sopc/lunwen/filter/filter.vwf"
Info: Overwriting simulation input file with simulation results
    Info: A backup of filter.vwf called filter.sim_ori.vwf has been created in the db folder
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Warning: Found clock-sensitive change during active clock edge at time 45.0 ns on register "|filter|reg8:reg8_23|out_data[0]"
Warning: Found clock-sensitive change during active clock edge at time 45.0 ns on register "|filter|reg8:reg8_22|out_data[1]"
Warning: Found clock-sensitive change during active clock edge at time 45.0 ns on register "|filter|reg8:reg8_22|out_data[0]"
Warning: Found clock-sensitive change during active clock edge at time 45.0 ns on register "|filter|reg8:reg8_21|out_data[0]"
Warning: Found clock-sensitive change during active clock edge at time 75.0 ns on register "|filter|reg8:reg8_23|out_data[2]"
Warning: Found clock-sensitive change during active clock edge at time 75.0 ns on register "|filter|reg8:reg8_23|out_data[1]"
Warning: Found clock-sensitive change during active clock edge at time 75.0 ns on register "|filter|reg8:reg8_21|out_data[1]"
Warning: Found clock-sensitive change during active clock edge at time 105.0 ns on register "|filter|reg8:reg8_22|out_data[3]"
Warning: Found clock-sensitive change during active clock edge at time 105.0 ns on register "|filter|reg8:reg8_22|out_data[2]"
Warning: Found clock-sensitive change during active clock edge at time 135.0 ns on register "|filter|reg8:reg8_21|out_data[2]"
Warning: Found clock-sensitive change during active clock edge at time 195.0 ns on register "|filter|reg8:reg8_23|out_data[4]"
Warning: Found clock-sensitive change during active clock edge at time 195.0 ns on register "|filter|reg8:reg8_23|out_data[3]"
Warning: Found clock-sensitive change during active clock edge at time 255.0 ns on register "|filter|reg8:reg8_21|out_data[3]"
Warning: Found clock-sensitive change during active clock edge at time 345.0 ns on register "|filter|reg8:reg8_22|out_data[5]"
Warning: Found clock-sensitive change during active clock edge at time 345.0 ns on register "|filter|reg8:reg8_22|out_data[4]"
Warning: Found clock-sensitive change during active clock edge at time 495.0 ns on register "|filter|reg8:reg8_21|out_data[4]"
Warning: Found clock-sensitive change during active clock edge at time 675.0 ns on register "|filter|reg8:reg8_23|out_data[6]"
Warning: Found clock-sensitive change during active clock edge at time 675.0 ns on register "|filter|reg8:reg8_23|out_data[5]"
Warning: Found clock-sensitive change during active clock edge at time 975.0 ns on register "|filter|reg8:reg8_21|out_data[5]"
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      74.15 %
Info: Number of transitions in simulation is 4030
Info: Vector file filter.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 19 warnings
    Info: Peak virtual memory: 111 megabytes
    Info: Processing ended: Mon Feb 23 19:26:01 2009
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02