filter.sim.rpt

来自「图像处理技术中3*3模板的滤波电路的VHDL实现.」· RPT 代码 · 共 454 行 · 第 1/5 页

; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~64 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~64 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~65 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~65 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~66 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~66 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~67 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~67 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~68 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~68 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~69 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~69 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~70 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~70 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~71 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~71 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~72 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~72 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~74 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~74 ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~76 ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~76 ; out0             ;
; |filter|count3:count31|Add0~10                                              ; |filter|count3:count31|Add0~10                                              ; out0             ;
; |filter|count3:count31|Equal0~33                                            ; |filter|count3:count31|Equal0~33                                            ; out0             ;
+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                             ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+
; Node Name                                                                       ; Output Port Name                                                                ; Output Port Type ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+
; |filter|in_data1[7]                                                             ; |filter|in_data1[7]                                                             ; regout           ;
; |filter|out_data[8]                                                             ; |filter|out_data[8]                                                             ; pin_out          ;
; |filter|out_data[9]                                                             ; |filter|out_data[9]                                                             ; pin_out          ;
; |filter|in_data[7]                                                              ; |filter|in_data[7]                                                              ; out              ;
; |filter|add_1p:add9|s[9]                                                        ; |filter|add_1p:add9|s[9]                                                        ; regout           ;
; |filter|add_1p:add9|s[8]                                                        ; |filter|add_1p:add9|s[8]                                                        ; regout           ;
; |filter|add_1p:add9|l4[0]                                                       ; |filter|add_1p:add9|l4[0]                                                       ; regout           ;
; |filter|add_1p:add9|l3[1]                                                       ; |filter|add_1p:add9|l3[1]                                                       ; regout           ;
; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|carry_eqn[0]~1 ; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|carry_eqn[0]~1 ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|sum_eqn[1]     ; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|sum_eqn[1]     ; out0             ;
; |filter|add_1p:add9|lpm_ff:reg_4|dffs[0]                                        ; |filter|add_1p:add9|lpm_ff:reg_4|dffs[0]                                        ; regout           ;
; |filter|add_1p:add9|lpm_ff:reg_3|dffs[1]                                        ; |filter|add_1p:add9|lpm_ff:reg_3|dffs[1]                                        ; regout           ;
; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|carry_eqn[1]~1 ; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|carry_eqn[1]~1 ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|carry_eqn[0]~2 ; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|carry_eqn[0]~2 ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|sum_eqn[1]     ; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|sum_eqn[1]     ; out0             ;
; |filter|add8_9:add8_92|s[7]                                                     ; |filter|add8_9:add8_92|s[7]                                                     ; regout           ;
; |filter|add8_9:add8_92|l1[7]                                                    ; |filter|add8_9:add8_92|l1[7]                                                    ; regout           ;
; |filter|add8_9:add8_91|s[8]                                                     ; |filter|add8_9:add8_91|s[8]                                                     ; regout           ;
; |filter|add8_9:add8_91|l2[7]                                                    ; |filter|add8_9:add8_91|l2[7]                                                    ; regout           ;
; |filter|add8_9:add8_91|l1[7]                                                    ; |filter|add8_9:add8_91|l1[7]                                                    ; regout           ;
; |filter|reg8:reg8_23|out_data[7]                                                ; |filter|reg8:reg8_23|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_22|out_data[7]                                                ; |filter|reg8:reg8_22|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_21|out_data[7]                                                ; |filter|reg8:reg8_21|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_13|out_data[7]                                                ; |filter|reg8:reg8_13|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_12|out_data[7]                                                ; |filter|reg8:reg8_12|out_data[7]                                                ; regout           ;
; |filter|reg8:reg8_11|out_data[7]                                                ; |filter|reg8:reg8_11|out_data[7]                                                ; regout           ;
; |filter|add_1p:add9|lpm_add_sub:add_1|add_sub_qjc:auto_generated|op_1~44        ; |filter|add_1p:add9|lpm_add_sub:add_1|add_sub_qjc:auto_generated|op_1~44        ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_1|add_sub_qjc:auto_generated|op_1~70        ; |filter|add_1p:add9|lpm_add_sub:add_1|add_sub_qjc:auto_generated|op_1~70        ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~46     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~46     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~49     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~49     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~51     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~51     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~78     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~78     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~79     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~79     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~80     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~80     ; out0             ;
; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~81     ; |filter|add8_9:add8_91|lpm_add_sub:add_1|add_sub_rjc:auto_generated|op_1~81     ; out0             ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                             ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+
; Node Name                                                                       ; Output Port Name                                                                ; Output Port Type ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+
; |filter|in_data1[6]                                                             ; |filter|in_data1[6]                                                             ; regout           ;
; |filter|in_data1[7]                                                             ; |filter|in_data1[7]                                                             ; regout           ;
; |filter|out_data[7]                                                             ; |filter|out_data[7]                                                             ; pin_out          ;
; |filter|out_data[8]                                                             ; |filter|out_data[8]                                                             ; pin_out          ;
; |filter|out_data[9]                                                             ; |filter|out_data[9]                                                             ; pin_out          ;
; |filter|in_data[6]                                                              ; |filter|in_data[6]                                                              ; out              ;
; |filter|in_data[7]                                                              ; |filter|in_data[7]                                                              ; out              ;
; |filter|add_1p:add9|s[9]                                                        ; |filter|add_1p:add9|s[9]                                                        ; regout           ;
; |filter|add_1p:add9|s[8]                                                        ; |filter|add_1p:add9|s[8]                                                        ; regout           ;
; |filter|add_1p:add9|s[7]                                                        ; |filter|add_1p:add9|s[7]                                                        ; regout           ;
; |filter|add_1p:add9|l4[0]                                                       ; |filter|add_1p:add9|l4[0]                                                       ; regout           ;
; |filter|add_1p:add9|l3[0]                                                       ; |filter|add_1p:add9|l3[0]                                                       ; regout           ;
; |filter|add_1p:add9|l3[1]                                                       ; |filter|add_1p:add9|l3[1]                                                       ; regout           ;
; |filter|add_1p:add9|l2[6]                                                       ; |filter|add_1p:add9|l2[6]                                                       ; regout           ;
; |filter|add_1p:add9|l1[0]                                                       ; |filter|add_1p:add9|l1[0]                                                       ; regout           ;
; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|carry_eqn[0]~1 ; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|carry_eqn[0]~1 ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|sum_eqn[1]     ; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|sum_eqn[1]     ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|sum_eqn[0]     ; |filter|add_1p:add9|lpm_add_sub:add_3|add_sub_urc:auto_generated|sum_eqn[0]     ; out0             ;
; |filter|add_1p:add9|lpm_ff:reg_4|dffs[0]                                        ; |filter|add_1p:add9|lpm_ff:reg_4|dffs[0]                                        ; regout           ;
; |filter|add_1p:add9|lpm_ff:reg_3|dffs[1]                                        ; |filter|add_1p:add9|lpm_ff:reg_3|dffs[1]                                        ; regout           ;
; |filter|add_1p:add9|lpm_ff:reg_3|dffs[0]                                        ; |filter|add_1p:add9|lpm_ff:reg_3|dffs[0]                                        ; regout           ;
; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|carry_eqn[1]~1 ; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|carry_eqn[1]~1 ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|carry_eqn[0]~2 ; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|carry_eqn[0]~2 ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|sum_eqn[1]     ; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|sum_eqn[1]     ; out0             ;
; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|sum_eqn[0]~1   ; |filter|add_1p:add9|lpm_add_sub:add_2|add_sub_ljc:auto_generated|sum_eqn[0]~1   ; out0             ;