📄 moore1.rpt
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Device-Specific Information: d:\vhdl\moore1.rpt
moore1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - C 02 DFFE + 2 1 0 2 C_ST~1
- 5 - C 02 DFFE + 2 2 0 5 C_ST~2
- 4 - C 02 DFFE + 2 2 0 4 C_ST~3
- 3 - C 02 DFFE + 2 1 0 4 C_ST~4
- 1 - C 02 DFFE + 2 2 0 5 C_ST~5
- 1 - C 06 DFFE + 0 3 1 0 :5
- 2 - C 02 DFFE + 0 3 1 0 :7
- 4 - C 06 DFFE + 0 1 1 0 :9
- 7 - C 02 DFFE + 0 4 1 0 :11
- 6 - C 02 OR2 s 2 2 0 1 ~207~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\vhdl\moore1.rpt
moore1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 5/ 96( 5%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl\moore1.rpt
moore1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 CLK
Device-Specific Information: d:\vhdl\moore1.rpt
moore1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 RST
Device-Specific Information: d:\vhdl\moore1.rpt
moore1
** EQUATIONS **
CLK : INPUT;
DATAIN0 : INPUT;
DATAIN1 : INPUT;
RST : INPUT;
-- Node name is 'C_ST~1'
-- Equation name is 'C_ST~1', location is LC8_C2, type is buried.
C_ST~1 = DFFE( _EQ001, GLOBAL( CLK), GLOBAL(!RST), VCC, VCC);
_EQ001 = C_ST~2 & !DATAIN0 & !DATAIN1;
-- Node name is 'C_ST~2'
-- Equation name is 'C_ST~2', location is LC5_C2, type is buried.
C_ST~2 = DFFE( _EQ002, GLOBAL( CLK), GLOBAL(!RST), VCC, VCC);
_EQ002 = C_ST~1 & !DATAIN1
# C_ST~1 & !DATAIN0
# C_ST~3 & DATAIN0 & !DATAIN1;
-- Node name is 'C_ST~3'
-- Equation name is 'C_ST~3', location is LC4_C2, type is buried.
C_ST~3 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL(!RST), VCC, VCC);
_EQ003 = C_ST~2 & DATAIN1
# C_ST~2 & DATAIN0
# C_ST~4 & DATAIN0 & DATAIN1;
-- Node name is 'C_ST~4'
-- Equation name is 'C_ST~4', location is LC3_C2, type is buried.
C_ST~4 = DFFE( _EQ004, GLOBAL( CLK), GLOBAL(!RST), VCC, VCC);
_EQ004 = C_ST~4 & !DATAIN1
# C_ST~4 & !DATAIN0
# !C_ST~5 & !DATAIN0 & DATAIN1;
-- Node name is 'C_ST~5'
-- Equation name is 'C_ST~5', location is LC1_C2, type is buried.
C_ST~5 = DFFE( _EQ005, GLOBAL( CLK), GLOBAL(!RST), VCC, VCC);
_EQ005 = !DATAIN1 & _LC6_C2
# !DATAIN0 & _LC6_C2
# !C_ST~1 & _LC6_C2;
-- Node name is 'Q0'
-- Equation name is 'Q0', type is output
Q0 = _LC7_C2;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC4_C6;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC2_C2;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC1_C6;
-- Node name is ':5'
-- Equation name is '_LC1_C6', type is buried
_LC1_C6 = DFFE( _EQ006, GLOBAL( CLK), GLOBAL(!RST), VCC, VCC);
_EQ006 = !C_ST~2 & !C_ST~4
# !C_ST~5;
-- Node name is ':7'
-- Equation name is '_LC2_C2', type is buried
_LC2_C2 = DFFE( _EQ007, GLOBAL( CLK), GLOBAL(!RST), VCC, VCC);
_EQ007 = C_ST~3 & C_ST~5
# C_ST~4 & C_ST~5;
-- Node name is ':9'
-- Equation name is '_LC4_C6', type is buried
_LC4_C6 = DFFE( C_ST~2, GLOBAL( CLK), GLOBAL(!RST), VCC, VCC);
-- Node name is ':11'
-- Equation name is '_LC7_C2', type is buried
_LC7_C2 = DFFE( _EQ008, GLOBAL( CLK), GLOBAL(!RST), VCC, VCC);
_EQ008 = !C_ST~2 & !C_ST~3
# C_ST~4
# !C_ST~5;
-- Node name is '~207~1'
-- Equation name is '~207~1', location is LC6_C2, type is buried.
-- synthesized logic cell
_LC6_C2 = LCELL( _EQ009);
_EQ009 = !C_ST~3 & C_ST~5
# C_ST~5 & DATAIN0 & !DATAIN1
# !C_ST~3 & !DATAIN0 & DATAIN1;
Project Information d:\vhdl\moore1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,098K
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