moore1.vhd

来自「有限状态机及其设计技术是实用数字系统设计中的重要组成部分,也是实现高效可靠逻辑控」· VHDL 代码 · 共 37 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MOORE1 IS
  PORT (DATAIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        CLK,RST:IN STD_LOGIC;
         Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END MOORE1;
ARCHITECTURE behav OF MOORE1 IS
   TYPE ST_TYPE IS (ST0,ST1,ST2,ST3,ST4);
    SIGNAL C_ST:ST_TYPE;
     BEGIN
 PROCESS(CLK,RST)
  BEGIN
 IF RST='1'THEN C_ST<=ST0;Q<="0000";
   ELSIF CLK'EVENT AND CLK='1'THEN
    CASE C_ST IS
     WHEN ST0=>IF DATAIN="10" THEN C_ST<=ST1;
       ELSE C_ST<=ST0;END IF;
       Q<="1001";
     WHEN ST1 =>IF DATAIN="11"THEN C_ST<=ST2;
          ELSE C_ST<=ST1;END IF;
          Q<="0101";
     WHEN ST2 =>IF DATAIN="01"THEN C_ST<=ST3;
          ELSE C_ST<=ST0;END IF;
          Q<="1100";
     WHEN ST3 =>IF DATAIN="00"THEN C_ST<=ST4;
          ELSE C_ST<=ST2;END IF;
          Q<="0010";
     WHEN ST4 =>IF DATAIN="11"THEN C_ST<=ST0;
          ELSE C_ST<=ST3;END IF;
          Q<="1001";
     WHEN OTHERS=>C_ST<=ST0;
    END CASE;
   END IF;
  END PROCESS;
END behav;