bin_to_gray.vhd

来自「格雷码计数器」· VHDL 代码 · 共 35 行

--　　二进制码->格雷码（编码）：
--    从最右边一位起，依次将每一位与左边一位异或(XOR)，
--    作为对应格雷码该位的值，最左边一位不变.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity bin_to_gray is
generic (n : integer := 3);
port (
      reset : in  std_logic;
	  bin   : in  std_logic_vector(n downto 0);
	  gray  : out std_logic_vector(n downto 0) 
	 );
end bin_to_gray;

architecture behav of bin_to_gray is
  signal temp1,temp2 : std_logic_vector(n downto 0);
begin
  temp1 <= bin;
  process(reset,temp1)
    variable i : integer range 0 to n-1 := 0;
  begin
    if reset = '1' then
      temp2 <= (others => '0');
	else
      for i in 0 to n-1 loop
        temp2(i) <= temp1(i+1) xor temp1(i);     
      end loop;
      temp2(n) <= temp1(n);
    end if;
  end process;
  gray <= temp2;
end behav;