bin_cnt.vhd

来自「格雷码计数器」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity bin_cnt is
generic (n : integer := 3);
port (
      clk     : in  std_logic;
      bin_in  : in  std_logic_vector(n downto 0);
      bin_cnt : out std_logic_vector(n downto 0)
     );
end bin_cnt;

architecture behave of bin_cnt is

  signal bin_cnt_temp : std_logic_vector(n downto 0);

begin
  
  process(clk)
  begin
  if clk'event and clk = '1' then
    bin_cnt_temp <= bin_in + '1';
  end if;
  end process;
  bin_cnt <= bin_cnt_temp;

end behave;