watch.tan.qmsg

运用VHDL语言编写的秒表程序

{ "Info" "ITDB_FULL_TCO_RESULT" "cp2 sel\[5\] selsig\[5\] 20.000 ns register " "Info: tco from clock \"cp2\" to destination pin \"sel\[5\]\" through register \"selsig\[5\]\" is 20.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 source 10.400 ns + Longest register " "Info: + Longest clock path from clock \"cp2\" to source register is 10.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns cp2 1 CLK PIN_43 23 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 23; CLK Node = 'cp2'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cp2 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns count\[10\] 2 REG LC4_A20 17 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC4_A20; Fanout = 17; REG Node = 'count\[10\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { cp2 count[10] } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 10.400 ns selsig\[5\] 3 REG LC1_B2 2 " "Info: 3: + IC(4.000 ns) + CELL(0.000 ns) = 10.400 ns; Loc. = LC1_B2; Fanout = 2; REG Node = 'selsig\[5\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { count[10] selsig[5] } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 37.50 % ) " "Info: Total cell delay = 3.900 ns ( 37.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.500 ns ( 62.50 % ) " "Info: Total interconnect delay = 6.500 ns ( 62.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.400 ns" { cp2 count[10] selsig[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.400 ns" { cp2 cp2~out count[10] selsig[5] } { 0.000ns 0.000ns 2.500ns 4.000ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 81 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.500 ns + Longest register pin " "Info: + Longest register to pin delay is 8.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns selsig\[5\] 1 REG LC1_B2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B2; Fanout = 2; REG Node = 'selsig\[5\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { selsig[5] } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 81 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(5.100 ns) 8.500 ns sel\[5\] 2 PIN PIN_62 0 " "Info: 2: + IC(3.400 ns) + CELL(5.100 ns) = 8.500 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'sel\[5\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.500 ns" { selsig[5] sel[5] } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 60.00 % ) " "Info: Total cell delay = 5.100 ns ( 60.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns ( 40.00 % ) " "Info: Total interconnect delay = 3.400 ns ( 40.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.500 ns" { selsig[5] sel[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.500 ns" { selsig[5] sel[5] } { 0.000ns 3.400ns } { 0.000ns 5.100ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.400 ns" { cp2 count[10] selsig[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "10.400 ns" { cp2 cp2~out count[10] selsig[5] } { 0.000ns 0.000ns 2.500ns 4.000ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.500 ns" { selsig[5] sel[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "8.500 ns" { selsig[5] sel[5] } { 0.000ns 3.400ns } { 0.000ns 5.100ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 20 16:45:52 2008 " "Info: Processing ended: Tue May 20 16:45:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}