watch.tan.qmsg

运用VHDL语言编写的秒表程序

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "segsig\[0\] " "Warning: Node \"segsig\[0\]\" is a latch" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segsig\[1\] " "Warning: Node \"segsig\[1\]\" is a latch" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segsig\[2\] " "Warning: Node \"segsig\[2\]\" is a latch" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segsig\[3\] " "Warning: Node \"segsig\[3\]\" is a latch" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segsig\[4\] " "Warning: Node \"segsig\[4\]\" is a latch" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segsig\[5\] " "Warning: Node \"segsig\[5\]\" is a latch" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segsig\[6\] " "Warning: Node \"segsig\[6\]\" is a latch" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 79 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "cp2 " "Info: Assuming node \"cp2\" is an undefined clock" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 11 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cp2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "beginstop " "Info: Assuming node \"beginstop\" is an undefined clock" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 8 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "beginstop" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cp1 " "Info: Detected ripple clock \"cp1\" as buffer" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 25 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cp1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "count\[10\] " "Info: Detected ripple clock \"count\[10\]\" as buffer" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 22 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "count\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "cp2 register lpm_counter:num2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] register num6\[3\] 50.25 MHz 19.9 ns Internal " "Info: Clock \"cp2\" has Internal fmax of 50.25 MHz between source register \"lpm_counter:num2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"num6\[3\]\" (period= 19.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.300 ns + Longest register register " "Info: + Longest register to register delay is 16.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:num2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC7_B18 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_B18; Fanout = 3; REG Node = 'lpm_counter:num2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns Equal2~31 2 COMB LC1_B18 7 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC1_B18; Fanout = 7; COMB Node = 'Equal2~31'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Equal2~31 } "NODE_NAME" } } { "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 7.500 ns _~0 3 COMB LC5_B13 5 " "Info: 3: + IC(2.300 ns) + CELL(2.300 ns) = 7.500 ns; Loc. = LC5_B13; Fanout = 5; COMB Node = '_~0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.600 ns" { Equal2~31 _~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 10.400 ns _~1 4 COMB LC1_B13 5 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 10.400 ns; Loc. = LC1_B13; Fanout = 5; COMB Node = '_~1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { _~0 _~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.800 ns) 14.500 ns num6\[0\]~4 5 COMB LC6_B15 4 " "Info: 5: + IC(2.300 ns) + CELL(1.800 ns) = 14.500 ns; Loc. = LC6_B15; Fanout = 4; COMB Node = 'num6\[0\]~4'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.100 ns" { _~1 num6[0]~4 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 16.300 ns num6\[3\] 6 REG LC1_B15 3 " "Info: 6: + IC(0.600 ns) + CELL(1.200 ns) = 16.300 ns; Loc. = LC1_B15; Fanout = 3; REG Node = 'num6\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { num6[0]~4 num6[3] } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.900 ns ( 60.74 % ) " "Info: Total cell delay = 9.900 ns ( 60.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.400 ns ( 39.26 % ) " "Info: Total interconnect delay = 6.400 ns ( 39.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.300 ns" { lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Equal2~31 _~0 _~1 num6[0]~4 num6[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "16.300 ns" { lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Equal2~31 _~0 _~1 num6[0]~4 num6[3] } { 0.000ns 0.600ns 2.300ns 0.600ns 2.300ns 0.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.800ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 destination 11.100 ns + Shortest register " "Info: + Shortest clock path from clock \"cp2\" to destination register is 11.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns cp2 1 CLK PIN_43 23 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 23; CLK Node = 'cp2'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cp2 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns cp1 2 REG LC1_A20 27 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_A20; Fanout = 27; REG Node = 'cp1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { cp2 cp1 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 11.100 ns num6\[3\] 3 REG LC1_B15 3 " "Info: 3: + IC(4.700 ns) + CELL(0.000 ns) = 11.100 ns; Loc. = LC1_B15; Fanout = 3; REG Node = 'num6\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.700 ns" { cp1 num6[3] } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 35.14 % ) " "Info: Total cell delay = 3.900 ns ( 35.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns ( 64.86 % ) " "Info: Total interconnect delay = 7.200 ns ( 64.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.100 ns" { cp2 cp1 num6[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "11.100 ns" { cp2 cp2~out cp1 num6[3] } { 0.000ns 0.000ns 2.500ns 4.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "cp2 source 11.100 ns - Longest register " "Info: - Longest clock path from clock \"cp2\" to source register is 11.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns cp2 1 CLK PIN_43 23 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 23; CLK Node = 'cp2'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cp2 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns cp1 2 REG LC1_A20 27 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_A20; Fanout = 27; REG Node = 'cp1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.600 ns" { cp2 cp1 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.700 ns) + CELL(0.000 ns) 11.100 ns lpm_counter:num2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\] 3 REG LC7_B18 3 " "Info: 3: + IC(4.700 ns) + CELL(0.000 ns) = 11.100 ns; Loc. = LC7_B18; Fanout = 3; REG Node = 'lpm_counter:num2_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.700 ns" { cp1 lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 35.14 % ) " "Info: Total cell delay = 3.900 ns ( 35.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.200 ns ( 64.86 % ) " "Info: Total interconnect delay = 7.200 ns ( 64.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.100 ns" { cp2 cp1 lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "11.100 ns" { cp2 cp2~out cp1 lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns 4.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.100 ns" { cp2 cp1 num6[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "11.100 ns" { cp2 cp2~out cp1 num6[3] } { 0.000ns 0.000ns 2.500ns 4.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.100 ns" { cp2 cp1 lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "11.100 ns" { cp2 cp2~out cp1 lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns 4.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.300 ns" { lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Equal2~31 _~0 _~1 num6[0]~4 num6[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "16.300 ns" { lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] Equal2~31 _~0 _~1 num6[0]~4 num6[3] } { 0.000ns 0.600ns 2.300ns 0.600ns 2.300ns 0.600ns } { 0.000ns 2.300ns 2.300ns 2.300ns 1.800ns 1.200ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.100 ns" { cp2 cp1 num6[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "11.100 ns" { cp2 cp2~out cp1 num6[3] } { 0.000ns 0.000ns 2.500ns 4.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.100 ns" { cp2 cp1 lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "11.100 ns" { cp2 cp2~out cp1 lpm_counter:num2_rtl_1|alt_counter_f10ke:wysi_counter|q[3] } { 0.000ns 0.000ns 2.500ns 4.700ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "beginstop register register beginstop1 beginstop1 125.0 MHz Internal " "Info: Clock \"beginstop\" Internal fmax is restricted to 125.0 MHz between source register \"beginstop1\" and destination register \"beginstop1\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register register " "Info: + Longest register to register delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns beginstop1 1 REG LC8_B22 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B22; Fanout = 6; REG Node = 'beginstop1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { beginstop1 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 1.800 ns beginstop1 2 REG LC8_B22 6 " "Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC8_B22; Fanout = 6; REG Node = 'beginstop1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { beginstop1 beginstop1 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.200 ns ( 66.67 % ) " "Info: Total cell delay = 1.200 ns ( 66.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 33.33 % ) " "Info: Total interconnect delay = 0.600 ns ( 33.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { beginstop1 beginstop1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { beginstop1 beginstop1 } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "beginstop destination 7.500 ns + Shortest register " "Info: + Shortest clock path from clock \"beginstop\" to destination register is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns beginstop 1 CLK PIN_5 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_5; Fanout = 1; CLK Node = 'beginstop'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { beginstop } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 7.500 ns beginstop1 2 REG LC8_B22 6 " "Info: 2: + IC(4.000 ns) + CELL(0.000 ns) = 7.500 ns; Loc. = LC8_B22; Fanout = 6; REG Node = 'beginstop1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { beginstop beginstop1 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 46.67 % ) " "Info: Total cell delay = 3.500 ns ( 46.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 53.33 % ) " "Info: Total interconnect delay = 4.000 ns ( 53.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { beginstop beginstop1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.500 ns" { beginstop beginstop~out beginstop1 } { 0.000ns 0.000ns 4.000ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "beginstop source 7.500 ns - Longest register " "Info: - Longest clock path from clock \"beginstop\" to source register is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns beginstop 1 CLK PIN_5 1 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_5; Fanout = 1; CLK Node = 'beginstop'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { beginstop } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.000 ns) 7.500 ns beginstop1 2 REG LC8_B22 6 " "Info: 2: + IC(4.000 ns) + CELL(0.000 ns) = 7.500 ns; Loc. = LC8_B22; Fanout = 6; REG Node = 'beginstop1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { beginstop beginstop1 } "NODE_NAME" } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 46.67 % ) " "Info: Total cell delay = 3.500 ns ( 46.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 53.33 % ) " "Info: Total interconnect delay = 4.000 ns ( 53.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { beginstop beginstop1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.500 ns" { beginstop beginstop~out beginstop1 } { 0.000ns 0.000ns 4.000ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { beginstop beginstop1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.500 ns" { beginstop beginstop~out beginstop1 } { 0.000ns 0.000ns 4.000ns } { 0.000ns 3.500ns 0.000ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { beginstop beginstop1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.500 ns" { beginstop beginstop~out beginstop1 } { 0.000ns 0.000ns 4.000ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 27 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.800 ns" { beginstop1 beginstop1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.800 ns" { beginstop1 beginstop1 } { 0.000ns 0.600ns } { 0.000ns 1.200ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { beginstop beginstop1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.500 ns" { beginstop beginstop~out beginstop1 } { 0.000ns 0.000ns 4.000ns } { 0.000ns 3.500ns 0.000ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.500 ns" { beginstop beginstop1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "7.500 ns" { beginstop beginstop~out beginstop1 } { 0.000ns 0.000ns 4.000ns } { 0.000ns 3.500ns 0.000ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { beginstop1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { beginstop1 } {  } {  } } } { "watch.vhd" "" { Text "F:/U盘备份/新建文件夹/vhdl/秒表/秒表1/watch.vhd" 27 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}