📄 watch.drc.rpt
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Design Assistant report for watch
Tue May 20 16:49:29 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Design Assistant Summary
3. Design Assistant Settings
4. Critical Violations
5. High Violations
6. Medium Violations
7. Information only Violations
8. Design Assistant Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------+
; Design Assistant Summary ;
+-----------------------------------+-------------------------------------+
; Design Assistant Status ; Analyzed - Tue May 20 16:49:29 2008 ;
; Revision Name ; watch ;
; Top-level Entity Name ; watch ;
; Family ; FLEX10K ;
; Total Critical Violations ; 7 ;
; Total High Violations ; 1 ;
; Total Medium Violations ; 3 ;
; Total Information only Violations ; 50 ;
+-----------------------------------+-------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; Option ; Setting ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
; Design Assistant mode ; Post-Synthesis ;
; Threshold value for clock net not mapped to clock spines rule ; 25 ;
; Minimum number of node fan-out ; 30 ;
; Maximum number of nodes to report ; 50 ;
; Gated clock should be implemented according to Altera standard scheme (C101) ; On ;
; Logic cell should not be used to generate inverted clock (C102) ; On ;
; Input clock pin should fan out to only one set of clock gating logic (C103) ; On ;
; Clock signal source should drive only input clock ports (C104) ; On ;
; Clock signal should be a global signal (C105) (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On ;
; Clock signal source should not drive registers that are triggered by different clock edges (C106) ; On ;
; Combinational logic used as reset signal should be synchronized (R101) ; On ;
; External reset should be synchronized using two cascaded registers (R102) ; On ;
; External reset should be correctly synchronized (R103) ; On ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized (R104) ; On ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized (R105) ; On ;
; Nodes with more than specified number of fan-outs (T101) ; On ;
; Top nodes with highest fan-out (T102) ; On ;
; Design should not contain combinational loops (A101) ; On ;
; Register output should not drive its own control signal directly or through combinational logic (A102) ; On ;
; Design should not contain delay chains (A103) ; On ;
; Design should not contain ripple clock structures (A104) ; On ;
; Pulses should not be implemented asynchronously (A105) ; On ;
; Multiple pulses should not be generated in design (A106) ; On ;
; Design should not contain SR latches (A107) ; On ;
; Design should not contain latches (A108) ; On ;
; Combinational logic should not directly drive write enable signal of asynchronous RAM (A109) ; On ;
; Design should not contain asynchronous memory (A110) ; On ;
; Output enable and input of same tri-state node should not be driven by same signal source (S101) ; On ;
; Synchronous port and reset port of same register should not be driven by same signal source (S102) ; On ;
; Data bits are not synchronized when transferred between asynchronous clock domains (D101) ; On ;
; Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in receiving clock domain (D102) ; On ;
; Data bits are not correctly synchronized when transferred between asynchronous clock domains (D103) ; On ;
; Only one VREF pin should be assigned to HardCopy test pin in an I/O bank (H101) (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ;
; PLL drives multiple clock network types (H102) (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
+-----------------------------------------------------------------------------------------+
; Critical Violations ;
+-----------------------------------------------------------------------------+-----------+
; Rule name ; Name ;
+-----------------------------------------------------------------------------+-----------+
; Design should not contain combinational loops (A101) - Combinational loop 1 ; ;
; Combinational loop 1 ; segsig[0] ;
; Design should not contain combinational loops (A101) - Combinational loop 2 ; ;
; Combinational loop 2 ; segsig[1] ;
; Design should not contain combinational loops (A101) - Combinational loop 3 ; ;
; Combinational loop 3 ; segsig[2] ;
; Design should not contain combinational loops (A101) - Combinational loop 4 ; ;
; Combinational loop 4 ; segsig[3] ;
; Design should not contain combinational loops (A101) - Combinational loop 5 ; ;
; Combinational loop 5 ; segsig[4] ;
; Design should not contain combinational loops (A101) - Combinational loop 6 ; ;
; Combinational loop 6 ; segsig[5] ;
; Design should not contain combinational loops (A101) - Combinational loop 7 ; ;
; Combinational loop 7 ; segsig[6] ;
+-----------------------------------------------------------------------------+-----------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; High Violations ;
+---------------------------------------------------------------------------------------------------------+------------------------------------------------------------+
; Rule name ; Name ;
+---------------------------------------------------------------------------------------------------------+------------------------------------------------------------+
; Data bits are not synchronized when transferred between asynchronous clock domains (D101) - Structure 1 ; ;
; Structure 1 ; beginstop1 ;
; Structure 1 ; lpm_counter:num1_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ;
; Structure 1 ; lpm_counter:num1_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ;
; Structure 1 ; lpm_counter:num1_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ;
; Structure 1 ; lpm_counter:num1_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ;
+---------------------------------------------------------------------------------------------------------+------------------------------------------------------------+
+---------------------------------------------------------------------------------------+
; Medium Violations ;
+---------------------------------------------------------------------------+-----------+
; Rule name ; Name ;
+---------------------------------------------------------------------------+-----------+
; Clock signal source should drive only input clock ports (C104) ; count[10] ;
; Clock signal source should drive only input clock ports (C104) ; cp1 ;
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