ccd_dr.qsf

verilog HDL语言

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		ccd_dr_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY MAX7000AE
set_global_assignment -name DEVICE "EPM7064AELC44-4"
set_global_assignment -name TOP_LEVEL_ENTITY ccd_dr
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:48:30  JUNE 26, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name DEVICE_FILTER_PACKAGE ANY
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name VERILOG_FILE ccd_dr.v
set_global_assignment -name INCREMENTAL_COMPILATION OFF
set_location_assignment PIN_18 -to ccd_clk1
set_location_assignment PIN_19 -to ccd_clk2
set_location_assignment PIN_21 -to ccd_cp
set_location_assignment PIN_24 -to ccd_en
set_location_assignment PIN_25 -to ccd_rs
set_location_assignment PIN_26 -to ccd_sh
set_location_assignment PIN_43 -to clk
set_global_assignment -name VECTOR_WAVEFORM_FILE ccd_dr.vwf
set_global_assignment -name ZIP_VECTOR_WAVEFORM_FILE "../../../Documents and Settings/Administrator/桌面/ccd_dr.sim.cvwf"
set_global_assignment -name BDF_FILE Block1.bdf