designer.log

自己实用Verilog编写的UART程序

Imported the files:
   C:\Actelprj\ProASIC3\UART\synthesis\uart_test.edn
   C:\Actelprj\ProASIC3\UART\synthesis\uart_test_sdc.sdc

The Import command succeeded ( 00:00:05 )
The design C:\Actelprj\ProASIC3\UART\designer\impl1\uart_test.adb was last modified by software
version 7.3.0.29.
Opened an existing Libero design C:\Actelprj\ProASIC3\UART\designer\impl1\uart_test.adb.
'BA_NAME' set to 'uart_test_ba'

The Execute Script command succeeded ( 00:00:00 )
=====================================================================
Parameters used to run compile:
===============================

Family      : ProASIC3
Device      : A3P250
Package     : 208 PQFP
Source      : C:\Actelprj\ProASIC3\UART\synthesis\uart_test.edn
              C:\Actelprj\ProASIC3\UART\synthesis\uart_test_sdc.sdc
Format      : EDIF
Topcell     : uart_test
Speed grade : STD
Temp        : 0:25:70
Voltage     : 1.58:1.50:1.42

Keep Existing Physical Constraints : Yes
Keep Existing Timing Constraints   : Yes

pdc_abort_on_error                 : Yes
pdc_eco_display_unmatched_objects  : No
pdc_eco_max_warnings               : 10000

demote_globals                     : No
promote_globals                    : No
localclock_max_shared_instances    : 12
localclock_buffer_tree_max_fanout  : 12

combine_register                   : No
delete_buffer_tree                 : No

report_high_fanout_nets_limit      : 10

=====================================================================
Compile starts ...


Netlist Optimization Report
===========================

Optimized macros:
  - Dangling net drivers:   0
  - Buffers:                0
  - Inverters:              0
  - Tieoff:                 0
  - Logic combining:        19

    Total macros optimized  19

There were 0 error(s) and 0 warning(s) in this design.
=====================================================================

Reading previous post-compile physical placement constraints.


There were 0 error(s) and 0 warning(s).

=====================================================================
Compile report:
===============

    CORE                     Used:    277  Total:   6144   (4.51%)
    IO (W/ clocks)           Used:      3  Total:    151   (1.99%)
    Differential IO          Used:      0  Total:     34   (0.00%)
    GLOBAL (Chip+Quadrant)   Used:      1  Total:     18   (5.56%)
    PLL                      Used:      0  Total:      1   (0.00%)
    RAM/FIFO                 Used:      0  Total:      8   (0.00%)
    Low Static ICC           Used:      0  Total:      1   (0.00%)
    FlashROM                 Used:      0  Total:      1   (0.00%)
    User JTAG                Used:      0  Total:      1   (0.00%)

Global Information:

    Type            | Used   | Total
    ----------------|--------|-------------
    Chip global     | 1      | 6  (16.67%)
    Quadrant global | 0      | 12 (0.00%)

Core Information:

    Type    | Instances    | Core tiles
    --------|--------------|-----------
    COMB    | 197          | 197
    SEQ     | 80           | 80

I/O Function:

    Type                          | w/o register  | w/ register  | w/ DDR register
    ------------------------------|---------------|--------------|----------------
    Input I/O                     | 2             | 0            | 0
    Output I/O                    | 1             | 0            | 0
    Bidirectional I/O             | 0             | 0            | 0
    Differential Input I/O Pairs  | 0             | 0            | 0
    Differential Output I/O Pairs | 0             | 0            | 0

I/O Technology:

                                    |   Voltages    |             I/Os
    --------------------------------|-------|-------|-------|--------|--------------
    I/O Standard(s)                 | Vcci  | Vref  | Input | Output | Bidirectional
    --------------------------------|-------|-------|-------|--------|--------------
    LVTTL                           | 3.30v | N/A   | 2     | 1      | 0

Net information report:
=======================

The following nets have been assigned to a chip global resource:
    Fanout  Type          Name
    --------------------------
    69      CLK_NET       Net   : clock_c
                          Driver: clock_pad
                          Source: NETLIST

High fanout nets in the post compile netlist:
    Fanout  Type          Name
    --------------------------
    12      INT_NET       Net   : uartrec/StartF
                          Driver: uartrec/StartF
    10      CLK_NET       Net   : RI
                          Driver: uartrec/RI
    9       INT_NET       Net   : clkout
                          Driver: uartsend/clkout_0_a3
    9       INT_NET       Net   : WR
                          Driver: WR
    9       INT_NET       Net   : uartrec/UartBuff_1_sqmuxa
                          Driver: uartrec/bit_collect_16_e
    9       INT_NET       Net   : uartrec/N_48
                          Driver: uartrec/N_46_i_o3
    8       INT_NET       Net   : uartrec/count[0]
                          Driver: uartrec/count[0]
    8       INT_NET       Net   : uartrec/clkrec_0
                          Driver: uartrec/clkout_0
    8       INT_NET       Net   : uartrec/count_bit[1]
                          Driver: uartrec/count_bit[1]
    8       INT_NET       Net   : uartrec/un1_cnt10
                          Driver: uartrec/un1_cnt10

Nets that are candidates for clock assignment and the resulting fanout:
    Fanout  Type          Name
    --------------------------
    16      INT_NET       Net   : clkout
                          Driver: uartsend/clkout_0_a3
    12      INT_NET       Net   : uartrec/StartF
                          Driver: uartrec/StartF
    10      CLK_NET       Net   : RI
                          Driver: uartrec/RI
    9       INT_NET       Net   : WR
                          Driver: WR
    9       INT_NET       Net   : uartrec/UartBuff_1_sqmuxa
                          Driver: uartrec/bit_collect_16_e
    9       INT_NET       Net   : uartrec/N_48
                          Driver: uartrec/N_46_i_o3
    8       INT_NET       Net   : uartrec/count[0]
                          Driver: uartrec/count[0]
    8       INT_NET       Net   : uartrec/clkrec_0
                          Driver: uartrec/clkout_0
    8       INT_NET       Net   : uartrec/count_bit[1]
                          Driver: uartrec/count_bit[1]
    8       INT_NET       Net   : uartrec/un1_cnt10
                          Driver: uartrec/un1_cnt10


SDC Import: Starting final constraints validation...

Constraint System: There are no constraint to save in the database

The Compile command succeeded ( 00:00:05 )

Running I/O Bank Assigner.
 

I/O Bank Assigner completed successfully.
 

Running the Prelayout checker before global net placement.
Regions Consistency Checker completed.
IO Checker completed.

Planning global net placement...


Global net placement completed successfully.

Running the Prelayout checker after global net placement.
Regions Consistency Checker completed.
IO Checker completed.

desqdplacer V6_2_0.0 - 5/16/05
Design: C:\Actelprj\ProASIC3\UART\designer\impl1\uart_testStarted: Mon Apr 16 08:55:48 2007

IO & RAM improvement.
Core placement.
Core improvement.

Runtimes: IO Placement         = 0 seconds
          RAM Placement        = 0 seconds
          IO & RAM Improvement = 0 seconds
          Core Placement       = 1 seconds
          Core Improvement     = 3 seconds


desqdplacer completed successfully.

Design: C:\Actelprj\ProASIC3\UART\designer\impl1\uart_test
Finished: Mon Apr 16 08:55:52 2007
Total CPU Time:     00:00:04            Total Elapsed Time: 00:00:04
                        o - o - o - o - o - o


Timing-driven Router 
Design: uart_test                       Started: Mon Apr 16 08:55:55 2007

         
 Iterative improvement...

Timing-driven Router completed successfully.

Design: uart_test                       
Finished: Mon Apr 16 08:56:08 2007
Total CPU Time:     00:00:12            Total Elapsed Time: 00:00:13
                        o - o - o - o - o - o

Loading the Timing data for the design.
Finished loading the Timing data.
TIMER: Timing constraints requirements have been met.

The Layout command succeeded ( 00:00:37 )
Warning: File C:\Actelprj\ProASIC3\UART\designer\impl1\uart_test.stp already exists
         Do you want to replace it? [YES]

The Export-map command succeeded ( 00:00:27 )
Warning: Overwriting the existing file: ./uart_test.stp.
Wrote to the file: .\uart_test.stp

The Generate programming file command succeeded ( 00:00:29 )
Design saved to file C:\Actelprj\ProASIC3\UART\designer\impl1\uart_test.adb.
Design closed.