📄 uart_test.srr
字号:
uartrec.count[1] DFN1E0 Q Out 0.483 0.483 -
count[1] Net - - 0.655 - 3
uartrec.un7_count_1.I_5 XOR2 B In - 1.138 -
uartrec.un7_count_1.I_5 XOR2 Y Out 0.691 1.829 -
I_5_0 Net - - 0.841 - 4
uartrec.G_4_0 OR2A B In - 2.670 -
uartrec.G_4_0 OR2A Y Out 0.481 3.151 -
G_4_0 Net - - 0.279 - 1
uartrec.G_4_1 OR2A B In - 3.430 -
uartrec.G_4_1 OR2A Y Out 0.481 3.910 -
G_4_1 Net - - 0.279 - 1
uartrec.G_4 OR2 A In - 4.189 -
uartrec.G_4 OR2 Y Out 0.381 4.570 -
G_4 Net - - 0.469 - 2
uartrec.count_bit_5.G_1 NOR2A B In - 5.040 -
uartrec.count_bit_5.G_1 NOR2A Y Out 0.308 5.348 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.655 - 3
uartrec.count_bit_5.G_2 NOR2B B In - 6.003 -
uartrec.count_bit_5.G_2 NOR2B Y Out 0.466 6.469 -
G_2 Net - - 0.279 - 1
uartrec.count_bit_5.I_18 XOR2 B In - 6.748 -
uartrec.count_bit_5.I_18 XOR2 Y Out 0.691 7.438 -
count_bit_5[2] Net - - 0.469 - 2
uartrec.G_0 OA1 B In - 7.907 -
uartrec.G_0 OA1 Y Out 0.672 8.579 -
N_2 Net - - 0.469 - 2
uartrec.G_2 AO1A A In - 9.048 -
uartrec.G_2 AO1A Y Out 0.360 9.408 -
StartF_9 Net - - 0.279 - 1
uartrec.StartF DFN1E0 D In - 9.687 -
=========================================================================================
Total path delay (propagation time + setup) of 10.097 is 5.423(53.7%) logic and 4.675(46.3%) route.
Path information for path number 4:
Requested Period: 10.000
- Setup time: 0.310
= Required time: 9.690
- Propagation time: 9.707
= Slack (non-critical) : -0.017
Number of logic level(s): 9
Starting point: uartrec.count[0] / Q
Ending point: uartrec.count_bit[2] / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
uartrec.count[0] DFN1E0 Q Out 0.483 0.483 -
count[0] Net - - 1.470 - 8
uartrec.un7_count_1.I_5 XOR2 A In - 1.953 -
uartrec.un7_count_1.I_5 XOR2 Y Out 0.366 2.320 -
I_5_0 Net - - 0.841 - 4
uartrec.G_4_0 OR2A B In - 3.161 -
uartrec.G_4_0 OR2A Y Out 0.481 3.641 -
G_4_0 Net - - 0.279 - 1
uartrec.G_4_1 OR2A B In - 3.920 -
uartrec.G_4_1 OR2A Y Out 0.481 4.401 -
G_4_1 Net - - 0.279 - 1
uartrec.G_4 OR2 A In - 4.680 -
uartrec.G_4 OR2 Y Out 0.381 5.061 -
G_4 Net - - 0.469 - 2
uartrec.count_bit_5.G_1 NOR2A B In - 5.530 -
uartrec.count_bit_5.G_1 NOR2A Y Out 0.308 5.838 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.655 - 3
uartrec.count_bit_5.G_2 NOR2B B In - 6.493 -
uartrec.count_bit_5.G_2 NOR2B Y Out 0.466 6.959 -
G_2 Net - - 0.279 - 1
uartrec.count_bit_5.I_18 XOR2 B In - 7.238 -
uartrec.count_bit_5.I_18 XOR2 Y Out 0.691 7.929 -
count_bit_5[2] Net - - 0.469 - 2
uartrec.count_bit_0[2] MX2 A In - 8.398 -
uartrec.count_bit_0[2] MX2 Y Out 0.436 8.833 -
N_5 Net - - 0.279 - 1
uartrec.count_bit_1[2] OA1A C In - 9.112 -
uartrec.count_bit_1[2] OA1A Y Out 0.316 9.428 -
count_bit_1[2] Net - - 0.279 - 1
uartrec.count_bit[2] DFN1 D In - 9.707 -
=========================================================================================
Total path delay (propagation time + setup) of 10.017 is 4.718(47.1%) logic and 5.299(52.9%) route.
Path information for path number 5:
Requested Period: 10.000
- Setup time: 0.310
= Required time: 9.690
- Propagation time: 9.642
= Slack (non-critical) : 0.048
Number of logic level(s): 9
Starting point: uartrec.count[0] / Q
Ending point: uartrec.count_bit[2] / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
uartrec.count[0] DFN1E0 Q Out 0.483 0.483 -
count[0] Net - - 1.470 - 8
uartrec.un7_count_1.G_2 NOR3C C In - 1.953 -
uartrec.un7_count_1.G_2 NOR3C Y Out 0.491 2.444 -
G_2_0 Net - - 0.279 - 1
uartrec.un7_count_1.G_0 XOR2 A In - 2.723 -
uartrec.un7_count_1.G_0 XOR2 Y Out 0.366 3.090 -
G_0 Net - - 0.841 - 4
uartrec.G_4_1 OR2A A In - 3.931 -
uartrec.G_4_1 OR2A Y Out 0.405 4.336 -
G_4_1 Net - - 0.279 - 1
uartrec.G_4 OR2 A In - 4.615 -
uartrec.G_4 OR2 Y Out 0.381 4.996 -
G_4 Net - - 0.469 - 2
uartrec.count_bit_5.G_1 NOR2A B In - 5.465 -
uartrec.count_bit_5.G_1 NOR2A Y Out 0.308 5.773 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.655 - 3
uartrec.count_bit_5.G_2 NOR2B B In - 6.428 -
uartrec.count_bit_5.G_2 NOR2B Y Out 0.466 6.894 -
G_2 Net - - 0.279 - 1
uartrec.count_bit_5.I_18 XOR2 B In - 7.173 -
uartrec.count_bit_5.I_18 XOR2 Y Out 0.691 7.864 -
count_bit_5[2] Net - - 0.469 - 2
uartrec.count_bit_0[2] MX2 A In - 8.333 -
uartrec.count_bit_0[2] MX2 Y Out 0.436 8.768 -
N_5 Net - - 0.279 - 1
uartrec.count_bit_1[2] OA1A C In - 9.047 -
uartrec.count_bit_1[2] OA1A Y Out 0.316 9.363 -
count_bit_1[2] Net - - 0.279 - 1
uartrec.count_bit[2] DFN1 D In - 9.642 -
=========================================================================================
Total path delay (propagation time + setup) of 9.952 is 4.653(46.8%) logic and 5.299(53.2%) route.
##### END OF TIMING REPORT #####]
--------------------------------------------------------------------------------
Report for cell uart_test.verilog
Core Cell usage:
cell count area count*area
DFN1 52 1.0 52.0
XOR2 45 1.0 45.0
AND3 40 1.0 40.0
NOR2B 22 1.0 22.0
DFN1E1 21 1.0 21.0
NOR2A 15 1.0 15.0
NOR3C 15 1.0 15.0
NOR2 10 1.0 10.0
OA1A 9 1.0 9.0
NOR3B 9 1.0 9.0
MX2C 7 1.0 7.0
AND2 7 1.0 7.0
DFN1E0 7 1.0 7.0
MX2 5 1.0 5.0
OR2B 4 1.0 4.0
NOR3A 4 1.0 4.0
INV 3 1.0 3.0
GND 3 0.0 0.0
OR2A 3 1.0 3.0
VCC 3 0.0 0.0
OR3C 2 1.0 2.0
AO1A 2 1.0 2.0
BUFF 1 1.0 1.0
OA1C 1 1.0 1.0
XNOR2 1 1.0 1.0
OR3 1 1.0 1.0
AO1 1 1.0 1.0
OA1B 1 1.0 1.0
OR2 1 1.0 1.0
AX1C 1 1.0 1.0
AX1 1 1.0 1.0
OA1 1 1.0 1.0
AOI1B 1 1.0 1.0
NOR3 1 1.0 1.0
MAJ3 1 1.0 1.0
OAI1 1 1.0 1.0
----- ----------
TOTAL 302 296.0
IO Cell usage:
cell count
INBUF 1
CLKBUF 1
OUTBUF 1
-----
TOTAL 3
RAM/ROM Usage Summary
Block Rams : 0 of 8 (0%)
Mapper successful!
Process took 0h:00m:07s realtime, 0h:00m:02s cputime
# Mon Apr 16 08:48:07 2007
###########################################################]
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -