📄 uart_test.srr
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Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 0.953
= Slack (non-critical) : 8.638
Number of logic level(s): 0
Starting point: WR_R1 / Q
Ending point: WR_R2 / D
The start point is clocked by send|clkout_inferred_clock [rising] on pin CLK
The end point is clocked by send|clkout_inferred_clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------
WR_R1 DFN1 Q Out 0.483 0.483 -
WR_R1 Net - - 0.469 - 2
WR_R2 DFN1 D In - 0.953 -
=============================================================================
Total path delay (propagation time + setup) of 1.362 is 0.893(65.6%) logic and 0.469(34.4%) route.
====================================
Detailed Report for Clock: uart_test|clock
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------
uartrec.count[0] uart_test|clock DFN1E0 Q count[0] 0.483 -0.588
uartrec.count[1] uart_test|clock DFN1E0 Q count[1] 0.483 -0.097
uartrec.count[2] uart_test|clock DFN1E0 Q count[2] 0.483 0.494
uartrec.count[3] uart_test|clock DFN1E0 Q count[3] 0.483 1.115
uartrec.cnt[4] uart_test|clock DFN1 Q cnt[4] 0.483 1.291
uartrec.cnt[12] uart_test|clock DFN1 Q cnt[12] 0.483 1.295
uartrec.cnt[6] uart_test|clock DFN1 Q cnt[6] 0.483 1.302
uartrec.cnt[9] uart_test|clock DFN1 Q cnt[9] 0.483 1.402
uartrec.cnt[5] uart_test|clock DFN1 Q cnt[5] 0.483 1.466
uartrec.cnt[7] uart_test|clock DFN1 Q cnt[7] 0.483 1.573
===========================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------
uartrec.StartF uart_test|clock DFN1E0 D StartF_9 9.590 -0.588
uartrec.count_bit[2] uart_test|clock DFN1 D count_bit_1[2] 9.690 -0.017
uartrec.UartBuff[1] uart_test|clock DFN1E1 E N_85_i 9.650 0.223
uartrec.UartBuff[2] uart_test|clock DFN1E1 E N_87_i 9.650 0.223
uartrec.UartBuff[3] uart_test|clock DFN1E1 E N_89_i 9.650 0.223
uartrec.UartBuff[4] uart_test|clock DFN1E1 E N_91_i 9.650 0.223
uartrec.UartBuff[5] uart_test|clock DFN1E1 E N_93_i 9.650 0.223
uartrec.UartBuff[6] uart_test|clock DFN1E1 E N_95_i 9.650 0.223
uartrec.UartBuff[7] uart_test|clock DFN1E1 E N_97_i 9.650 0.223
uartrec.UartBuff[8] uart_test|clock DFN1E1 E N_99_i 9.650 0.223
======================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 10.178
= Slack (critical) : -0.588
Number of logic level(s): 9
Starting point: uartrec.count[0] / Q
Ending point: uartrec.StartF / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
uartrec.count[0] DFN1E0 Q Out 0.483 0.483 -
count[0] Net - - 1.470 - 8
uartrec.un7_count_1.I_5 XOR2 A In - 1.953 -
uartrec.un7_count_1.I_5 XOR2 Y Out 0.366 2.320 -
I_5_0 Net - - 0.841 - 4
uartrec.G_4_0 OR2A B In - 3.161 -
uartrec.G_4_0 OR2A Y Out 0.481 3.641 -
G_4_0 Net - - 0.279 - 1
uartrec.G_4_1 OR2A B In - 3.920 -
uartrec.G_4_1 OR2A Y Out 0.481 4.401 -
G_4_1 Net - - 0.279 - 1
uartrec.G_4 OR2 A In - 4.680 -
uartrec.G_4 OR2 Y Out 0.381 5.061 -
G_4 Net - - 0.469 - 2
uartrec.count_bit_5.G_1 NOR2A B In - 5.530 -
uartrec.count_bit_5.G_1 NOR2A Y Out 0.308 5.838 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.655 - 3
uartrec.count_bit_5.G_2 NOR2B B In - 6.493 -
uartrec.count_bit_5.G_2 NOR2B Y Out 0.466 6.959 -
G_2 Net - - 0.279 - 1
uartrec.count_bit_5.I_18 XOR2 B In - 7.238 -
uartrec.count_bit_5.I_18 XOR2 Y Out 0.691 7.929 -
count_bit_5[2] Net - - 0.469 - 2
uartrec.G_0 OA1 B In - 8.398 -
uartrec.G_0 OA1 Y Out 0.672 9.070 -
N_2 Net - - 0.469 - 2
uartrec.G_2 AO1A A In - 9.539 -
uartrec.G_2 AO1A Y Out 0.360 9.899 -
StartF_9 Net - - 0.279 - 1
uartrec.StartF DFN1E0 D In - 10.178 -
=========================================================================================
Total path delay (propagation time + setup) of 10.588 is 5.099(48.2%) logic and 5.489(51.8%) route.
Path information for path number 2:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 10.113
= Slack (non-critical) : -0.523
Number of logic level(s): 9
Starting point: uartrec.count[0] / Q
Ending point: uartrec.StartF / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
uartrec.count[0] DFN1E0 Q Out 0.483 0.483 -
count[0] Net - - 1.470 - 8
uartrec.un7_count_1.G_2 NOR3C C In - 1.953 -
uartrec.un7_count_1.G_2 NOR3C Y Out 0.491 2.444 -
G_2_0 Net - - 0.279 - 1
uartrec.un7_count_1.G_0 XOR2 A In - 2.723 -
uartrec.un7_count_1.G_0 XOR2 Y Out 0.366 3.090 -
G_0 Net - - 0.841 - 4
uartrec.G_4_1 OR2A A In - 3.931 -
uartrec.G_4_1 OR2A Y Out 0.405 4.336 -
G_4_1 Net - - 0.279 - 1
uartrec.G_4 OR2 A In - 4.615 -
uartrec.G_4 OR2 Y Out 0.381 4.996 -
G_4 Net - - 0.469 - 2
uartrec.count_bit_5.G_1 NOR2A B In - 5.465 -
uartrec.count_bit_5.G_1 NOR2A Y Out 0.308 5.773 -
DWACT_ADD_CI_0_TMP[0] Net - - 0.655 - 3
uartrec.count_bit_5.G_2 NOR2B B In - 6.428 -
uartrec.count_bit_5.G_2 NOR2B Y Out 0.466 6.894 -
G_2 Net - - 0.279 - 1
uartrec.count_bit_5.I_18 XOR2 B In - 7.173 -
uartrec.count_bit_5.I_18 XOR2 Y Out 0.691 7.864 -
count_bit_5[2] Net - - 0.469 - 2
uartrec.G_0 OA1 B In - 8.333 -
uartrec.G_0 OA1 Y Out 0.672 9.005 -
N_2 Net - - 0.469 - 2
uartrec.G_2 AO1A A In - 9.474 -
uartrec.G_2 AO1A Y Out 0.360 9.834 -
StartF_9 Net - - 0.279 - 1
uartrec.StartF DFN1E0 D In - 10.113 -
=========================================================================================
Total path delay (propagation time + setup) of 10.523 is 5.033(47.8%) logic and 5.489(52.2%) route.
Path information for path number 3:
Requested Period: 10.000
- Setup time: 0.410
= Required time: 9.590
- Propagation time: 9.687
= Slack (non-critical) : -0.097
Number of logic level(s): 9
Starting point: uartrec.count[1] / Q
Ending point: uartrec.StartF / D
The start point is clocked by uart_test|clock [rising] on pin CLK
The end point is clocked by uart_test|clock [rising] on pin CLK
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------
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