testbnch.v

使用Libero提供的异步通信IP核实现UART通信

                end 
               else
                begin
                  passflag = passflag +1;
		  if (passflag == count) 
	           begin 
                     $display("THIS TEST IS PASSED\n"); 
	             $display("-----------------------------------------------------"); 
	           end
                end 
             end
         end 
    
      $display("Setting UART1 7bit, parity enabled, and even parity"); 
      // UART1 7bit, parity enabled, and even parity
      UARTconfig1_bit8 = 1'b0 ; 
      UARTconfig1_parity_en = 1'b1 ; 
      UARTconfig1_odd_n_even = 1'b0 ; 
      $display("Setting UART2 7bit, parity enabled, and odd parity"); 
      // UART2 7bit, parity enabled, and odd parity
      UARTconfig2_bit8 = 1'b0 ; 
      UARTconfig2_parity_en = 1'b1 ; 
      UARTconfig2_odd_n_even = 1'b1 ; 
      repeat (10) @(posedge clk); 
      begin 
        if (FIFO_DEPTH_16 == 1)
	  count = 16;
        else
	  count = 128;
      end
         $display("Testing parity error generation"); 
         // Initialiase test data
         tc = 0; 
         rc = 0; 
         i = 0; 
         
         begin
           for(i = 0; i <= count-1; i = i + 1)
             begin
               tdata[i] = i; 
               par_err[i] = 0; 
             end
         end

         while (rc < count)
         begin
            @(posedge clk); 
            if (tc < count)
            begin
               // Firstly See if the Transmitter is ready
               if (UARTstatus1_txrdy == 1'b1)
               begin
                  wdata = tdata[tc]; 
                  cpu_write(wdata);
                  tc = tc + 1; 
               end 
            end 
            if (RX_FIFO == 0)
             begin
               // Now See if any received data
               if (UARTstatus2_rxrdy == 1'b1)
                begin
                  par_err[rc] = UARTstatus2_parity_err; 
                  cpu_read;
                  rdata[rc] = UARTstatus2_data_out; 
                  rc = rc + 1; 
                end 
             end
            else
             begin
               if (UARTstatus2_parity_err == 1'b1)
                begin
                  par_err[rc] = UARTstatus2_parity_err; 
                  cpu_read;
                  rdata[rc] = UARTstatus2_data_out; 
                  rc = rc + 1; 
                end 
             end 
         end 
         
         begin 
           passflag = 0; 
           for(i = 0; i <= count - 1; i = i + 1)
             begin
               if (par_err[i] != 1)
                begin 
                  $display("THIS TEST IS FAILED\n"); 
	          $finish;
                end 
               else
                begin
                  passflag = passflag +1;
		  if (passflag == count) 
	           begin 
                     $display("THIS TEST IS PASSED\n"); 
	             $display("-----------------------------------------------------"); 
	           end
                end 
             end
         end 
    
      $display("Setting UART1 7bit, parity enabled, and odd parity"); 
      // UART1 7bit, parity enabled, and odd parity
      UARTconfig1_bit8 = 1'b0 ; 
      UARTconfig1_parity_en = 1'b1 ; 
      UARTconfig1_odd_n_even = 1'b1 ; 
      $display("Setting UART2 8bit, parity enabled, and even parity"); 
      // UART2 7bit, parity enabled, and even parity
      UARTconfig2_bit8 = 1'b0 ; 
      UARTconfig2_parity_en = 1'b1 ; 
      UARTconfig2_odd_n_even = 1'b0 ; 
      repeat (10) @(posedge clk); 
      begin 
        if (FIFO_DEPTH_16 == 1)
	  count = 16;
        else
	  count = 256;
      end
         $display("Testing parity error generation"); 
         // Initialiase test data
         tc = 0; 
         rc = 0; 
         i = 0; 
         
         begin
           for(i = 0; i <= count-1; i = i + 1)
             begin
               tdata[i] = i; 
               par_err[i] = 0; 
             end
         end

         while (rc < count)
         begin
            @(posedge clk); 
            if (tc < count)
            begin
               // Firstly See if the Transmitter is ready
               if (UARTstatus1_txrdy == 1'b1)
               begin
                  wdata = tdata[tc]; 
                  cpu_write(wdata);
                  tc = tc + 1; 
               end 
            end 
            if (RX_FIFO == 0)
             begin
               // Now See if any received data
               if (UARTstatus2_rxrdy == 1'b1)
                begin
                  par_err[rc] = UARTstatus2_parity_err; 
                  cpu_read;
                  rdata[rc] = UARTstatus2_data_out; 
                  rc = rc + 1; 
                end 
             end
            else
             begin
               if (UARTstatus2_parity_err == 1'b1)
                begin
                  par_err[rc] = UARTstatus2_parity_err; 
                  cpu_read;
                  rdata[rc] = UARTstatus2_data_out; 
                  rc = rc + 1; 
                end 
             end 
         end 
         
         begin 
           passflag = 0; 
           for(i = 0; i <= count - 1; i = i + 1)
             begin
               if (par_err[i] != 1)
                begin 
                  $display("THIS TEST IS FAILED\n"); 
	          $finish;
                end 
               else
                begin
                  passflag = passflag +1;
		  if (passflag == count) 
	           begin 
                     $display("THIS TEST IS PASSED\n"); 
	             $display("-----------------------------------------------------"); 
	           end
                end 
             end
         end 
    
      //---------------------------------
      // Testing Overflow circuitry
      //---------------------------------
      if (RX_FIFO == 0)
      begin
         $display("Setting UART1 8bit, parity enabled, and odd parity"); 
         UARTconfig1_bit8 = 1'b1 ; 
         UARTconfig1_parity_en = 1'b1 ; 
         UARTconfig1_odd_n_even = 1'b0 ; 
         $display("Setting UART2 8bit, parity enabled, and odd parity"); 
         UARTconfig2_bit8 = 1'b1 ; 
         UARTconfig2_parity_en = 1'b1 ; 
         UARTconfig2_odd_n_even = 1'b0 ; 
         repeat (100) @(posedge clk); 
         $display("Testing for RX data overflow"); 
         cpu_write(8'b10100101);
         repeat (5) @(posedge clk); 
         if (UARTstatus2_overflow == 1'b1)
         begin
            $display("Overflow set too early"); 
         end 
         if (UARTstatus1_txrdy == 1'b1)
         begin
            cpu_write(8'b01011010);
            @(posedge UARTstatus2_overflow); 
            repeat (10) @(posedge clk); 
         end
         else
         begin
            @(posedge UARTstatus1_txrdy); 
            repeat (10) @(posedge clk); 
            cpu_write(8'b01011010);
            @(posedge UARTstatus2_overflow); 
            repeat (10) @(posedge clk); 
         end 
         // Get the byte, should be the first one
         if (UARTstatus2_rxrdy == 1'b1)
         begin
            cpu_read;
         end
         else
         begin
            @(posedge UARTstatus2_rxrdy); 
            cpu_read;
         end 
         if (UARTstatus2_data_out != 8'b10100101)
         begin
            $display("THIS TEST IS FAILED\n"); 
	    $finish;
         end
         else
         begin
            $display("THIS TEST IS PASSED\n"); 
	    $display("-----------------------------------------------------"); 
         end 
         repeat (5) @(posedge clk); 
         cpu_write(8'b01011010);
      end 

     if (RX_FIFO == 1)
      begin
      $display("Setting UART1 Operating Mode 8 bit, parity enabled, and even parity"); 
      UARTconfig1_bit8 = 1'b1 ; 
      UARTconfig1_parity_en = 1'b1 ; 
      UARTconfig1_odd_n_even = 1'b0 ; 
      $display("Setting UART2 Operating Mode 8 bit, parity enabled, and even parity"); 
      UARTconfig2_bit8 = 1'b1 ; 
      UARTconfig2_parity_en = 1'b1 ; 
      UARTconfig2_odd_n_even = 1'b0 ; 
      repeat (10) @(posedge clk);
      begin 
        if (FIFO_DEPTH_16 == 1)
	  count = 16;
        else
	  count = 256;
      end
         tc = 0;
         rc = 0;
         $display("Testing for RX data overflow"); 
         // Initialiase test data
         begin
            for(i = 0; i <= count-1; i = i + 1)
            begin
               tdata[i] = i; 
            end
         end 
         while (tc < count)
          begin
           @(posedge clk); 
            if (tc < count)
            begin
               // Firstly See if the Transmitter is ready
               if (UARTstatus1_txrdy == 1'b1)
               begin
                 wdata = tdata[tc]; 
                 cpu_write(wdata);
                 tc = tc + 1; 
               end 
            end 
         end 
          // Now See if any received data
            @(posedge UARTstatus2_overflow); 
            begin
              cpu_read;
              rdata[0] = UARTstatus2_data_out; 
            end 
          end 
         // Verify that correct data received
          begin 
               if (rdata[0] != tdata[0])
                begin
                  $display("THIS TEST IS FAILED\n"); 
	          $finish;
                end 
               else
                begin
                  $display("THIS TEST IS PASSED\n"); 
	          $display("-----------------------------------------------------"); 
                end 
          end 
      
      $display("END OF SIMULATION"); 
      $display("ALL TESTS ARE PASSED"); 
      $finish; 
   end 


   //----------------------------------------------------------------
   // basic CPU read and write cycles 
   //       
   task cpu_write;
      input [7:0] data; 
       
      begin
        cpucontrol_sel1 = 1'b0 ; 
        cpucontrol_data = data ; 
        cpucontrol_WEn = 1'b0 ; 
        @(posedge clk); 
        cpucontrol_WEn = 1'b1 ; 
        @(posedge clk); 
        cpucontrol_sel1 = 1'b1 ; 
        @(posedge clk); 
      end
   endtask

   task cpu_read;
      begin
        cpucontrol_sel2 = 1'b0 ; 
        cpucontrol_OEn = 1'b0 ; 
        @(posedge clk); 
        cpucontrol_sel2 = 1'b1 ; 
        cpucontrol_OEn = 1'b1 ; 
        repeat (4) @(posedge clk); 
      end
   endtask

endmodule