_primary.vhd

来自「使用Libero提供的异步通信IP核实现UART通信」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity CUARTO0l is
    port(
        DATA            : in     vl_logic_vector(7 downto 0);
        Q               : out    vl_logic_vector(7 downto 0);
        WE              : in     vl_logic;
        RE              : in     vl_logic;
        WCLOCK          : in     vl_logic;
        RCLOCK          : in     vl_logic;
        FULL            : out    vl_logic;
        EMPTY           : out    vl_logic;
        RESET           : in     vl_logic;
        AEMPTY          : out    vl_logic;
        AFULL           : out    vl_logic;
        LEVEL           : in     vl_logic_vector(7 downto 0)
    );
end CUARTO0l;