testbnch.v

使用Libero提供的异步通信IP核实现UART通信

// ------------------------------------------------------------------------- --
// ------------------------------------------------------------------------- --
//                                                                           --
// File................: TESTBNCH.VHD                                        --
// Function............: Test bench for GENERIC UART                          --
// Version.............: 3.00                                                --
// Last Updated........: 05-25-05                                            --
// Component of........: None                                                --
// Components Required.: UART                                                 --
// Compilation Notes...:                                                     --
//                                                                           --
// Revision History:                                                         --
//   3.00:  added fifo verification
//   2.00:  improve report
//   1.01:  Initial design                                                   --
//   1.00:  Initial design                                                   --
//                                                                           --
//                                                                           --
// ------------------------------------------------------------------------- --
// ------------------------------------------------------------------------- --
`timescale  1ns/1ps

module testbnch ();

`include "../../../../coreparameters.v"

    //  1=fifo depth is 16 bytes, FIFO_DEPTH_16
    //  is used for the testbench purpose only to
    //  support the devices(SX-A, RTSX-S)

   // The following parameter is used only in the testbench
   parameter FIFO_DEPTH_16 = 0; 

   //-----------------------------------------------
   // component port listings
   //-----------------------------------------------
   //  1=with fifo operation mode
   //  1=with fifo operation mode
   //-----------------------------------------------
   // internal signals
   //-----------------------------------------------
   reg clk = 1'b0; 
   reg reset_n = 1'b0; 
   wire [7:0] UARTstatus1_data_out; 
   wire [7:0] UARTstatus2_data_out; 
   reg UARTconfig1_bit8; 
   reg UARTconfig1_parity_en; 
   reg UARTconfig1_odd_n_even; 
   reg UARTconfig2_bit8; 
   reg UARTconfig2_parity_en; 
   reg UARTconfig2_odd_n_even; 
   wire[7:0] cpudata; 
   wire txdata1; 
   wire rxdata1; 
   wire txdata2; 
   wire rxdata2; 
   wire[7:0] baud_val; 
   reg [7:0] cpucontrol_data;
   reg cpucontrol_sel1; 
   reg cpucontrol_sel2; 
   reg cpucontrol_WEn; 
   reg cpucontrol_OEn;
   reg [8:0] count; 
   reg [7:0] tdata[0:511] ; 
   reg [7:0] rdata[0:511] ; 
   reg[7:0] wdata; 
   reg [8:0] rc; 
   reg [8:0] tc; 
   reg [8:0] i; 
   reg [8:0] passflag; 
   reg [7:0] par_err[0:511]; 

   assign cpudata = cpucontrol_data ;
   //-----------------------------------------------
   // 2 Meg baud selection based on 33 MHZ clock
   //-----------------------------------------------
   assign baud_val = 8'b00000001 ;

   //-----------------------------------------------
   // drive clock
   //-----------------------------------------------
   always 
   begin
      #15; 
      clk = ~clk ; 
   end 
   //-----------------------------------------------
   // component instantiations
   //-----------------------------------------------

   COREUART #(.TX_FIFO(TX_FIFO), .RX_FIFO(RX_FIFO), .FAMILY(FAMILY)) make_UART1(.RESET_N(reset_n), .CLK(clk), .WEN(cpucontrol_WEn), .OEN(cpucontrol_OEn), .CSN(cpucontrol_sel1), .DATA_IN(cpudata), .RX(rxdata1), .BAUD_VAL(baud_val), .BIT8(UARTconfig1_bit8), .PARITY_EN(UARTconfig1_parity_en), .ODD_N_EVEN(UARTconfig1_odd_n_even), .PARITY_ERR(UARTstatus1_parity_err), .OVERFLOW(UARTstatus1_overflow), .TXRDY(UARTstatus1_txrdy), .RXRDY(UARTstatus1_rxrdy), .DATA_OUT(UARTstatus1_data_out), .TX(txdata1)); 

   COREUART #(.TX_FIFO(TX_FIFO), .RX_FIFO(RX_FIFO), .FAMILY(FAMILY)) make_UART2(.RESET_N(reset_n), .CLK(clk), .WEN(cpucontrol_WEn), .OEN(cpucontrol_OEn), .CSN(cpucontrol_sel2), .DATA_IN(cpudata), .RX(rxdata2), .BAUD_VAL(baud_val), .BIT8(UARTconfig2_bit8), .PARITY_EN(UARTconfig2_parity_en), .ODD_N_EVEN(UARTconfig2_odd_n_even), .PARITY_ERR(UARTstatus2_parity_err), .OVERFLOW(UARTstatus2_overflow), .TXRDY(UARTstatus2_txrdy), .RXRDY(UARTstatus2_rxrdy), .DATA_OUT(UARTstatus2_data_out), .TX(txdata2)); 
   assign rxdata1 = txdata2 ;
   assign rxdata2 = txdata1 ;

   initial 
   begin : xhdl_7
      // ALL TESTS BY DEFAULT TRANSMIT ON UART1 AND RECEIVE ON UART2
      $display("Actel UART Testbench  v2.00 "); 
      $display("--------------------------------------"); 
      $display(" "); 
      //----------------------------------
      // initial control signal conditions
      //----------------------------------
       cpucontrol_sel1 = 1'b1;
       cpucontrol_sel2 = 1'b1;
       cpucontrol_WEn = 1'b1;
       cpucontrol_OEn = 1'b1;
       cpucontrol_data = 8'b00000000;
      //-----------------------------------------------
      // drive the resets
      //-----------------------------------------------
      $display("Appling Reset"); 
      reset_n = 1'b0 ; 
      repeat (10) @(posedge clk); 
      @(posedge clk); 
      #100; 
      reset_n = 1'b1 ; 
      $display("Setting UART1 Operating Mode 8 bit, parity enabled, and even parity"); 
      UARTconfig1_bit8 = 1'b1 ; 
      UARTconfig1_parity_en = 1'b1 ; 
      UARTconfig1_odd_n_even = 1'b0 ; 
      $display("Setting UART2 Operating Mode 8 bit, parity enabled, and even parity"); 
      UARTconfig2_bit8 = 1'b1 ; 
      UARTconfig2_parity_en = 1'b1 ; 
      UARTconfig2_odd_n_even = 1'b0 ; 
      repeat (10) @(posedge clk);
      begin 
        if (FIFO_DEPTH_16 == 1)
	  count = 16;
        else
	  count = 256;
      end
         tc = 0;
         rc = 0;
         $display("Testing Continuous Data Stream UART1 to UART2"); 
         // Initialiase test data
         begin
            for(i = 0; i <= count-1; i = i + 1)
            begin
               tdata[i] = i; 
            end
         end 
         while (rc < count)
          begin
           @(posedge clk); 
            if (tc < count)
            begin
               // Firstly See if the Transmitter is ready
               if (UARTstatus1_txrdy == 1'b1)
               begin
                 wdata = tdata[tc]; 
                 cpu_write(wdata);
                 tc = tc + 1; 
               end 
            end 
          // Now See if any received data
            if (UARTstatus2_rxrdy == 1'b1)
            begin
              cpu_read;
              rdata[rc] = UARTstatus2_data_out; 
              rc = rc + 1; 
            end 
          end 
         // Verify that correct data received
          begin 
            passflag = 0; 
            for(i = 0; i <= count - 1; i = i + 1)
            begin
               if (rdata[i] != tdata[i])
                begin
                  $display("THIS TEST IS FAILED\n"); 
	          $finish;
                end 
               else
                begin
                  passflag = passflag +1;
		  if (passflag == count)
	           begin 
                     $display("THIS TEST IS PASSED\n"); 
	             $display("-----------------------------------------------------"); 
	           end
                end 
            end
          end 
         
      
      $display("Setting UART1 Operating Mode 8 bit, parity enabled, and odd parity"); 
      UARTconfig1_bit8 = 1'b1 ; 
      UARTconfig1_parity_en = 1'b1 ; 
      UARTconfig1_odd_n_even = 1'b1 ; 
      $display("Setting UART2 Operating Mode 8 bit, parity enabled, and odd parity"); 
      UARTconfig2_bit8 = 1'b1 ; 
      UARTconfig2_parity_en = 1'b1 ; 
      UARTconfig2_odd_n_even = 1'b1 ; 
      repeat (10) @(posedge clk); 
      begin 
        if (FIFO_DEPTH_16 == 1)
	  count = 16;
        else
	  count = 256;
      end
         tc = 0;
         rc = 0;
         $display("Testing Continuous Data Stream UART1 to UART2"); 
         // Initialiase test data
         begin
            for(i = 0; i <= count-1; i = i + 1)
            begin
               tdata[i] = i; 
            end
         end 
         while (rc < count)
          begin
           @(posedge clk); 
            if (tc < count)
            begin
               // Firstly See if the Transmitter is ready
               if (UARTstatus1_txrdy == 1'b1)
               begin
                 wdata = tdata[tc]; 
                 cpu_write(wdata);
                 tc = tc + 1; 
               end 
            end 
          // Now See if any received data
            if (UARTstatus2_rxrdy == 1'b1)
            begin
              cpu_read;
              rdata[rc] = UARTstatus2_data_out; 
              rc = rc + 1; 
            end 
          end 
         // Verify that correct data received
          begin 
            passflag = 0; 
            for(i = 0; i <= count - 1; i = i + 1)
            begin
               if (rdata[i] != tdata[i])
                begin
                  $display("THIS TEST IS FAILED\n"); 
	          $finish;
                end 
               else
                begin
                  passflag = passflag +1;
		  if (passflag == count) 
	           begin 
                     $display("THIS TEST IS PASSED\n"); 
	             $display("-----------------------------------------------------"); 
	           end
                end 
            end
          end 
         
      $display("Setting UART1 Operating Mode 7 bit, parity enabled, and even parity"); 
      UARTconfig1_bit8 = 1'b0 ; 
      UARTconfig1_parity_en = 1'b1 ; 
      UARTconfig1_odd_n_even = 1'b0 ; 
      $display("Setting UART2 Operating Mode 7 bit, parity enabled, and even parity"); 
      UARTconfig2_bit8 = 1'b0 ; 
      UARTconfig2_parity_en = 1'b1 ; 
      UARTconfig2_odd_n_even = 1'b0 ; 
      repeat (10) @(posedge clk); 
      begin 
        if (FIFO_DEPTH_16 == 1)
	  count = 16;
        else
	  count = 128;
      end
         tc = 0;
         rc = 0;
         $display("Testing Continuous Data Stream UART1 to UART2"); 
         // Initialiase test data
         begin
            for(i = 0; i <= count-1; i = i + 1)
            begin
               tdata[i] = i; 
            end
         end 
         while (rc < count)
          begin
           @(posedge clk); 
            if (tc < count)
            begin
               // Firstly See if the Transmitter is ready
               if (UARTstatus1_txrdy == 1'b1)
               begin
                 wdata = tdata[tc]; 
                 cpu_write(wdata);
                 tc = tc + 1; 
               end 
            end 
          // Now See if any received data
            if (UARTstatus2_rxrdy == 1'b1)
            begin
              cpu_read;
              rdata[rc] = UARTstatus2_data_out; 
              rc = rc + 1; 
            end 
          end 
         // Verify that correct data received
          begin 
            passflag = 0; 
            for(i = 0; i <= count - 1; i = i + 1)
            begin
               if (rdata[i] != tdata[i])
                begin
                  $display("THIS TEST IS FAILED\n"); 
	          $finish;
                end 
               else
                begin
                  passflag = passflag +1;
		  if (passflag == count) 
	           begin 
                     $display("THIS TEST IS PASSED\n"); 
	             $display("-----------------------------------------------------"); 
	           end
                end 
            end
          end 
         
      $display("Setting UART1 Operating Mode 7 bit, parity enabled, and odd parity"); 
      UARTconfig1_bit8 = 1'b0 ; 
      UARTconfig1_parity_en = 1'b1 ; 
      UARTconfig1_odd_n_even = 1'b1 ; 
      $display("Setting UART2 Operating Mode 7 bit, parity enabled, and odd parity"); 
      UARTconfig2_bit8 = 1'b0 ; 
      UARTconfig2_parity_en = 1'b1 ; 
      UARTconfig2_odd_n_even = 1'b1 ; 
      repeat (10) @(posedge clk); 
      begin 
        if (FIFO_DEPTH_16 == 1)
	  count = 16;
        else
	  count = 128;
      end
         tc = 0;
         rc = 0;
         $display("Testing Continuous Data Stream UART1 to UART2"); 
         // Initialiase test data
         begin
            for(i = 0; i <= count-1; i = i + 1)
            begin
               tdata[i] = i;