_primary.vhd

来自「使用Libero提供的异步通信IP核实现UART通信」· VHDL 代码 · 共 27 行

library verilog;
use verilog.vl_types.all;
entity uart_ctrl is
    generic(
        WRITE_STEP1     : integer := 0;
        WRITE_STEP2     : integer := 1;
        WRITE_STEP3     : integer := 2;
        WRITE_STEP4     : integer := 3;
        WRITE_STEP5     : integer := 4;
        RECEIVE_STEP1   : integer := 0;
        RECEIVE_STEP2   : integer := 1;
        RECEIVE_STEP3   : integer := 2;
        RECEIVE_STEP4   : integer := 3
    );
    port(
        CLK             : in     vl_logic;
        RST             : in     vl_logic;
        DATA_TRF        : out    vl_logic_vector(7 downto 0);
        DATA_RCE        : out    vl_logic_vector(7 downto 0);
        RE              : out    vl_logic;
        WE              : out    vl_logic;
        CS              : out    vl_logic;
        TX              : out    vl_logic;
        RX              : in     vl_logic
    );
end uart_ctrl;