_primary.vhd

使用Libero提供的异步通信IP核实现UART通信

library verilog;
use verilog.vl_types.all;
entity PLL_33 is
    port(
        POWERDOWN       : in     vl_logic;
        CLKA            : in     vl_logic;
        LOCK            : out    vl_logic;
        GLA             : out    vl_logic
    );
end PLL_33;