_primary.vhd

来自「使用Libero提供的异步通信IP核实现UART通信」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity fifo_256x8 is
    generic(
        LEVEL           : integer := 255
    );
    port(
        DO              : out    vl_logic_vector(7 downto 0);
        RCLOCK          : in     vl_logic;
        WCLOCK          : in     vl_logic;
        DI              : in     vl_logic_vector(7 downto 0);
        WRB             : in     vl_logic;
        RDB             : in     vl_logic;
        RESET           : in     vl_logic;
        FULL            : out    vl_logic;
        EMPTY           : out    vl_logic
    );
end fifo_256x8;