_primary.vhd

来自「使用Libero提供的异步通信IP核实现UART通信」· VHDL 代码 · 共 29 行

library verilog;
use verilog.vl_types.all;
entity COREUART is
    generic(
        TX_FIFO         : integer := 0;
        RX_FIFO         : integer := 0;
        FAMILY          : integer := 15
    );
    port(
        RESET_N         : in     vl_logic;
        CLK             : in     vl_logic;
        WEN             : in     vl_logic;
        OEN             : in     vl_logic;
        CSN             : in     vl_logic;
        DATA_IN         : in     vl_logic_vector(7 downto 0);
        RX              : in     vl_logic;
        BAUD_VAL        : in     vl_logic_vector(7 downto 0);
        BIT8            : in     vl_logic;
        PARITY_EN       : in     vl_logic;
        ODD_N_EVEN      : in     vl_logic;
        PARITY_ERR      : out    vl_logic;
        OVERFLOW        : out    vl_logic;
        TXRDY           : out    vl_logic;
        RXRDY           : out    vl_logic;
        DATA_OUT        : out    vl_logic_vector(7 downto 0);
        TX              : out    vl_logic
    );
end COREUART;