_primary.vhd

来自「使用Libero提供的异步通信IP核实现UART通信」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity PLL_33 is
    port(
        PLL_33_VCC      : in     vl_logic;
        PLL_33_GND      : in     vl_logic;
        PLL_33M_i       : out    vl_logic;
        CLK_c           : in     vl_logic
    );
end PLL_33;