_primary.vhd

来自「使用Libero提供的异步通信IP核实现UART通信」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity COREUART_0s_0s_15s is
    port(
        data_out_reg    : out    vl_logic_vector(7 downto 0);
        DATA_TRF_c      : in     vl_logic_vector(7 downto 0);
        RE_c            : in     vl_logic;
        RXRDY           : out    vl_logic;
        RX_c            : in     vl_logic;
        TXRDY           : out    vl_logic;
        TX_c            : out    vl_logic;
        WE_c            : in     vl_logic;
        RST_c           : in     vl_logic;
        PLL_33M         : in     vl_logic
    );
end COREUART_0s_0s_15s;