_primary.vhd

来自「使用Libero提供的异步通信IP核实现UART通信」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity Tx_async_0s_0s_1s_2s_3s_4s_5s_6s is
    port(
        tx_hold_reg     : in     vl_logic_vector(7 downto 0);
        TX_c            : out    vl_logic;
        RST_c           : in     vl_logic;
        PLL_33M         : in     vl_logic;
        WE_c            : in     vl_logic;
        TXRDY           : out    vl_logic;
        xmit_pulse_i    : in     vl_logic
    );
end Tx_async_0s_0s_1s_2s_3s_4s_5s_6s;