_primary.vhd

来自「使用Libero提供的异步通信IP核实现UART通信」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity Rx_async_0s_0s_1s_2s is
    port(
        data_out_reg    : out    vl_logic_vector(7 downto 0);
        RX_c            : in     vl_logic;
        RST_c           : in     vl_logic;
        PLL_33M         : in     vl_logic;
        RXRDY           : out    vl_logic;
        RE_c            : in     vl_logic;
        baud_clock      : in     vl_logic
    );
end Rx_async_0s_0s_1s_2s;