freqsyn.v

使用Verilog语言编写的使用SPI总线设置频率LM2346,可通过设置其R寄存器对其输出频率进行设置（需相应的射频电路相配合）。

/********************FREQSYN*********************************
**模块名称：FREQSYN(Frequency Synthesizer)(PLL)
**功能描述：上电后控制频率合成器LM2346使其输出为特定频率
*********************************************************/

module FREQSYN(
            CLOCK,      //系统时钟，使用系统的时钟
            RESET,      //上电复位
            FPGA_RESET, //FPGA软复位
            PLL_CLK,    //提供给PLL时钟
            PLL_DATA,   //PLL数据
            PLL_N_REG,  //PLL N寄存器低16位
            PLL_INI_FLAG,   //开始设置PLL标志位
            PLL_LE      //PLL数据使能
            //PLL_TEST //PLL自检，1为有效，0为失锁
            );

/**********************PLL管脚定义*******************/
input   CLOCK;
input   RESET;
input   FPGA_RESET;
input   PLL_INI_FLAG;
input   [15:0]  PLL_N_REG;

output  PLL_CLK;
output  PLL_DATA;
output  PLL_LE;

/********************寄存器线网声明*******************/
reg [6:0]   PLL_ClkBuf;                         //时钟缓冲
reg [1:0]   PLL_CmdCount;                       //发送命令计数器
reg [4:0]   PLL_BitCount;                       //发送位计数器
reg [17:0]  PLL_Cmd;                            //命令发送寄存器
reg [17:0]  PLL_Nreg;                           //PLL N寄存器

reg     PLL_CmdOut;                             //命令发送位寄存器
wire    PLL_Clock;                             //PLL   SPI输出时钟
reg     Clk_Buf;                                //PLL时钟缓冲
reg     Clk_En;                                 //时钟使能 


reg     PLL_Start_Flag1,PLL_Start_Flag2;
wire    PLL_Start_Flag;

reg     PLL_LE_Flag;


//parameter PLL_Nreg = 18'b000100111000100000;    //4'h4E20;         //N register,500M
//parameter PLL_Nreg = 18'b000101000101000000;    //4'h4E20;         //N register,520M
//parameter PLL_Nreg = 18'b000101000101001000;    //4'h4E20;         //N register,520.2M
//parameter PLL_Nreg = 18'b000101000101010000;    //4'h4E20;         //N register,520.4M
//parameter PLL_Nreg = 18'b000101000100111000;    //4'h4E20;         //N register,519.8M
//parameter PLL_Nreg = 18'b000101000100010000;    //4'h4E20;         //N register,518.8M
parameter PLL_Rreg = 18'b000001000010000001;    //4'h1081;         //R register

/***********************PLL时钟*************************/

always @(posedge CLOCK)
begin
    PLL_ClkBuf = PLL_ClkBuf + 7'b1;         //提供PLL芯片SPI总线时钟。FPGA时钟为24.576M
end

assign  PLL_Clock = PLL_ClkBuf[6];        //系统时钟16*4分频，为1.536MHz

always @(posedge CLOCK)
begin
    if(Clk_En)
        Clk_Buf = PLL_Clock;               //当有数据时再输出时钟
    else
        Clk_Buf = 1'b0;
end

assign  PLL_CLK = Clk_Buf;


/***********************PLL开始初始化标志*************************/

always@(posedge CLOCK)				//通过PLL_START产生一个PLL开始初始化信号	
begin
     if(PLL_INI_FLAG)
     begin
        if(!PLL_Start_Flag)
        begin
            PLL_Nreg = {2'b00,PLL_N_REG[15:0]};     //将上层PLL的N寄存器的低16位与高两位结合，组成PLL的N寄存器值
            PLL_Start_Flag1 = ~PLL_Start_Flag2;
        end
     end
end
assign PLL_Start_Flag = PLL_Start_Flag1^PLL_Start_Flag2;	


/***********************主程序，FPGA向PLL传送命令*****************/

always@(negedge PLL_Clock)
begin
    if(!RESET | FPGA_RESET)
    begin
        PLL_LE_Flag = 1'b1;             //上电复位后将LE管脚置为高电平
        PLL_CmdCount = 2'b0;            //计数器清零
        PLL_BitCount = 5'b0;
        Clk_En = 1'b0;                  //时钟禁止
        PLL_Start_Flag2 = PLL_Start_Flag1;      //清PLL_Start_Flag
    end
    else
    begin
        if(PLL_Start_Flag)
        begin   //if1
            if(PLL_LE_Flag)
            begin   //if2
                if(PLL_CmdCount >= 2'b10)
                begin
                    PLL_CmdCount = 2'b0;
                    PLL_Start_Flag2 = PLL_Start_Flag1;      //清PLL_Start_Flag
                    PLL_LE_Flag = 1'b0;
                    PLL_CmdOut = 1'b0;
                end
                else
                begin
                    if(PLL_CmdCount == 2'b0)
                        PLL_Cmd = PLL_Nreg;                 //将待发送命令放入命令缓冲
                    else if(PLL_CmdCount == 2'b1)
                        PLL_Cmd = PLL_Rreg;
                    PLL_CmdCount = PLL_CmdCount + 2'b1;
                    PLL_LE_Flag = 1'b0;
                end
            end     
            else    //else if2
            begin
                if(PLL_BitCount >= 5'b10010)
                begin
                    Clk_En = 1'b0;
                    PLL_BitCount = 5'b0;
                    PLL_LE_Flag = 1'b1;
                end
                else
                begin
                    Clk_En = 1'b1;
                    PLL_CmdOut = PLL_Cmd[5'b10001 - PLL_BitCount];
                    PLL_BitCount = PLL_BitCount + 5'b1;
                end
            end     //end if2
        end     //endif1
    end
end

assign  PLL_DATA = PLL_CmdOut;
assign  PLL_LE = PLL_LE_Flag;

endmodule