automake.log

vlsi UART referene, use UART0_3

ispLEVER Auto-Make Log File
---------------------------

Updating: Hierarchy
Start to record tcl script...
Finished recording TCL script.

Starting: 'C:\ispTOOLS7_0\ispcpld\bin\vlog2jhd.exe "uart_regs.v" -p "C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog" -pf xp.v -noglib -predefine uart_version2.h -setting uart_version2.sty'

-- Analyzing Verilog file C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog/xp.v
-- Analyzing Verilog file uart_version2.h
-- Analyzing Verilog file uart_regs.v
uart_regs.v(230): ERROR: cannot open include file uart_defines.v (VERI-1245)
uart_regs.v(274): WARNING: use of undefined macro UART_ADDR_WIDTH (VERI-1158)
uart_regs.v(301): WARNING: use of undefined macro UART_FIFO_COUNTER_W (VERI-1158)
uart_regs.v(366): WARNING: use of undefined macro UART_MC_RTS (VERI-1158)
uart_regs.v(366): ERROR: syntax error near ] (VERI-1137)
uart_regs.v(369): WARNING: use of undefined macro UART_LC_DL (VERI-1158)
uart_regs.v(369): ERROR: syntax error near ] (VERI-1137)
uart_regs.v(373): ERROR: syntax error near ] (VERI-1137)
uart_regs.v(374): ERROR: syntax error near ] (VERI-1137)
uart_regs.v(386): WARNING: use of undefined macro UART_FIFO_REC_WIDTH (VERI-1158)
uart_regs.v(442): WARNING: use of undefined macro UART_REG_RB (VERI-1158)
uart_regs.v(442): ERROR: syntax error near : (VERI-1137)
uart_regs.v(443): WARNING: use of undefined macro UART_REG_IE (VERI-1158)
uart_regs.v(443): ERROR: syntax error near : (VERI-1137)
uart_regs.v(444): WARNING: use of undefined macro UART_REG_II (VERI-1158)
uart_regs.v(444): ERROR: syntax error near : (VERI-1137)
uart_regs.v(445): WARNING: use of undefined macro UART_REG_LC (VERI-1158)
uart_regs.v(445): ERROR: syntax error near : (VERI-1137)
uart_regs.v(446): WARNING: use of undefined macro UART_REG_LS (VERI-1158)
uart_regs.v(446): ERROR: syntax error near : (VERI-1137)
uart_regs.v(447): WARNING: use of undefined macro UART_REG_MS (VERI-1158)
uart_regs.v(447): ERROR: syntax error near : (VERI-1137)
uart_regs.v(448): WARNING: use of undefined macro UART_REG_SR (VERI-1158)
uart_regs.v(448): ERROR: syntax error near : (VERI-1137)
uart_regs.v(463): ERROR: syntax error near && (VERI-1137)
uart_regs.v(473): ERROR: syntax error near && (VERI-1137)
uart_regs.v(474): ERROR: syntax error near && (VERI-1137)
uart_regs.v(475): ERROR: syntax error near && (VERI-1137)
uart_regs.v(476): ERROR: syntax error near && (VERI-1137)
uart_regs.v(477): WARNING: use of undefined macro UART_REG_TR (VERI-1158)
uart_regs.v(477): ERROR: syntax error near && (VERI-1137)
uart_regs.v(513): ERROR: syntax error near ) (VERI-1137)
-- Sorry, too many errors..
Done: completed successfully.

Starting: 'C:\ispTOOLS7_0\ispcpld\bin\vlog2jhd.exe "uart_transmitter.v" -p "C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog" -pf xp.v -noglib -predefine uart_version2.h -setting uart_version2.sty'

-- Analyzing Verilog file C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog/xp.v
-- Analyzing Verilog file uart_version2.h
-- Analyzing Verilog file uart_transmitter.v
uart_transmitter.v(155): ERROR: cannot open include file uart_defines.v (VERI-1245)
uart_transmitter.v(169): WARNING: use of undefined macro UART_FIFO_COUNTER_W (VERI-1158)
uart_transmitter.v(268): WARNING: use of undefined macro UART_LC_PE (VERI-1158)
uart_transmitter.v(268): ERROR: syntax error near ] (VERI-1137)
uart_transmitter.v(272): ERROR: syntax error near else (VERI-1137)
uart_transmitter.v(274): WARNING: use of undefined macro UART_LC_EP (VERI-1158)
uart_transmitter.v(274): ERROR: syntax error near ] (VERI-1137)
uart_transmitter.v(276): ERROR: syntax error near 2 (VERI-1137)
uart_transmitter.v(277): ERROR: syntax error near 2 (VERI-1137)
uart_transmitter.v(278): ERROR: syntax error near 2 (VERI-1137)
uart_transmitter.v(279): ERROR: syntax error near endcase (VERI-1137)
uart_transmitter.v(304): WARNING: use of undefined macro UART_LC_SB (VERI-1158)
uart_transmitter.v(304): ERROR: syntax error near ] (VERI-1137)
uart_transmitter.v(306): ERROR: syntax error near 3 (VERI-1137)
uart_transmitter.v(307): ERROR: syntax error near default (VERI-1137)
uart_transmitter.v(308): ERROR: syntax error near endcase (VERI-1137)
uart_transmitter.v(329): WARNING: use of undefined macro UART_LC_BC (VERI-1158)
uart_transmitter.v(329): ERROR: syntax error near ] (VERI-1137)
uart_transmitter.v(223): ERROR: tf_data_out is not declared (VERI-1128)
uart_transmitter.v(227): ERROR: tf_data_out is not declared (VERI-1128)
uart_transmitter.v(231): ERROR: tf_data_out is not declared (VERI-1128)
uart_transmitter.v(235): ERROR: tf_data_out is not declared (VERI-1128)
uart_transmitter.v(238): ERROR: tf_data_out is not declared (VERI-1128)
uart_transmitter.v(331): ERROR: module uart_transmitter ignored due to previous errors (VERI-1072)
-- Verilog file uart_transmitter.v ignored due to errors
Done: completed successfully.

Starting: 'C:\ispTOOLS7_0\ispcpld\bin\vlog2jhd.exe "uart_top.v" -p "C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog" -pf xp.v -noglib -predefine uart_version2.h -setting uart_version2.sty'

-- Analyzing Verilog file C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog/xp.v
-- Analyzing Verilog file uart_version2.h
-- Analyzing Verilog file uart_top.v
uart_top.v(141): ERROR: cannot open include file uart_defines.v (VERI-1245)
uart_top.v(169): WARNING: use of undefined macro UART_DATA_WIDTH (VERI-1158)
uart_top.v(169): ERROR: syntax error near ; (VERI-1137)
uart_top.v(170): WARNING: use of undefined macro UART_ADDR_WIDTH (VERI-1158)
uart_top.v(170): ERROR: syntax error near ; (VERI-1137)
uart_top.v(267): ERROR: port connections cannot be mixed ordered and named (VERI-1162)
uart_top.v(155): ERROR: data_i is not declared (VERI-1128)
uart_top.v(156): ERROR: data_o is not declared (VERI-1128)
uart_top.v(172): ERROR: port wb_clk_i is not defined (VERI-1171)
uart_top.v(175): ERROR: uart_addr_width is not declared (VERI-1128)
uart_top.v(181): ERROR: uart_addr_width is not declared (VERI-1128)
uart_top.v(182): ERROR: uart_addr_width is not declared (VERI-1128)
uart_top.v(183): ERROR: port dat_i is not defined (VERI-1171)
uart_top.v(184): ERROR: port dat_o is not defined (VERI-1171)
uart_top.v(303): ERROR: module uart_top ignored due to previous errors (VERI-1072)
-- Verilog file uart_top.v ignored due to errors
Done: completed successfully.

Starting: 'C:\ispTOOLS7_0\ispcpld\bin\vlog2jhd.exe "uart_sync_flops.v" -p "C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog" -pf xp.v -noglib -predefine uart_version2.h -setting uart_version2.sty'

-- Analyzing Verilog file C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog/xp.v
-- Analyzing Verilog file uart_version2.h
-- Analyzing Verilog file uart_sync_flops.v
uart_sync_flops.v(71): ERROR: cannot open include file timescale.v (VERI-1245)
uart_sync_flops.v(125): ERROR: module uart_sync_flops ignored due to previous errors (VERI-1072)
-- Verilog file uart_sync_flops.v ignored due to errors
Done: completed successfully.

Starting: 'C:\ispTOOLS7_0\ispcpld\bin\vlog2jhd.exe "uart_receiver.v" -p "C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog" -pf xp.v -noglib -predefine uart_version2.h -setting uart_version2.sty'

-- Analyzing Verilog file C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog/xp.v
-- Analyzing Verilog file uart_version2.h
-- Analyzing Verilog file uart_receiver.v
uart_receiver.v(199): ERROR: cannot open include file uart_defines.v (VERI-1245)
uart_receiver.v(214): WARNING: use of undefined macro UART_FIFO_COUNTER_W (VERI-1158)
uart_receiver.v(215): WARNING: use of undefined macro UART_FIFO_REC_WIDTH (VERI-1158)
uart_receiver.v(322): WARNING: use of undefined macro UART_LC_PE (VERI-1158)
uart_receiver.v(322): ERROR: syntax error near ] (VERI-1137)
uart_receiver.v(324): ERROR: syntax error near else (VERI-1137)
uart_receiver.v(329): ERROR: syntax error near else (VERI-1137)
uart_receiver.v(350): WARNING: use of undefined macro UART_LC_EP (VERI-1158)
uart_receiver.v(350): ERROR: syntax error near ] (VERI-1137)
uart_receiver.v(352): ERROR: syntax error near 2 (VERI-1137)
uart_receiver.v(353): ERROR: syntax error near 2 (VERI-1137)
uart_receiver.v(354): ERROR: syntax error near 2 (VERI-1137)
uart_receiver.v(355): ERROR: syntax error near endcase (VERI-1137)
uart_receiver.v(266): ERROR: rf_push is not declared (VERI-1128)
uart_receiver.v(267): ERROR: rf_data_in is not declared (VERI-1128)
uart_receiver.v(274): ERROR: rf_push is not declared (VERI-1128)
uart_receiver.v(275): ERROR: rf_data_in is not declared (VERI-1128)
uart_receiver.v(277): ERROR: break_error is not declared (VERI-1128)
uart_receiver.v(283): ERROR: rf_push is not declared (VERI-1128)
uart_receiver.v(377): ERROR: break_error is not declared (VERI-1128)
uart_receiver.v(379): ERROR: break_error is not declared (VERI-1128)
uart_receiver.v(380): ERROR: rf_data_in is not declared (VERI-1128)
uart_receiver.v(382): ERROR: rf_data_in is not declared (VERI-1128)
-- Sorry, too many errors..
Done: completed successfully.

Starting: 'C:\ispTOOLS7_0\ispcpld\bin\vlog2jhd.exe "uart_debug_if.v" -p "C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog" -pf xp.v -noglib -predefine uart_version2.h -setting uart_version2.sty'

-- Analyzing Verilog file C:\ispTOOLS7_0\ispcpld/../cae_library/synthesis/verilog/xp.v
-- Analyzing Verilog file uart_version2.h
-- Analyzing Verilog file uart_debug_if.v
uart_debug_if.v(90): ERROR: cannot open include file uart_defines.v (VERI-1245)
uart_debug_if.v(100): WARNING: use of undefined macro UART_ADDR_WIDTH (VERI-1158)
uart_debug_if.v(109): WARNING: use of undefined macro UART_FIFO_COUNTER_W (VERI-1158)
uart_debug_if.v(128): ERROR: module uart_debug_if ignored due to previous errors (VERI-1072)
-- Verilog file uart_debug_if.v ignored due to errors
Done: completed successfully.