uart_version2.lci

来自「vlsi UART referene, use UART0_3」· LCI 代码 · 共 64 行

[Device]
Family = mg5g00;
PartNumber = LFXP10C-4F388C;
Package = FPBGA388;
PartType = LFXP10C;
Speed = -4;
Operating_condition = COM;
Status = Production;

[Revision]
Parent = mg5g00.lci;
DATE = 2002;
TIME = 0:00:00;
Source_Format = Pure_Verilog_HDL;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]
NetList = VERILOG;

[IO Types]
layer = OFF;

[Pullup]

[Slewrate]

[Region]

[Timing Constraints]

[HSI Attributes]

[Input Delay]