uart_version2.syn

来自「vlsi UART referene, use UART0_3」· SYN 代码 · 共 22 行

JDF B
// Created by Version 7.0 
PROJECT uart_version2
DESIGN uart_version2 Normal
DEVKIT LFXP10C-4F388C
ENTRY Pure Verilog HDL
MODULE uart_regs.v
MODSTYLE uart_regs.v Normal
MODULE uart_sync_flops.v
MODSTYLE uart_sync_flops.v Normal
MODULE uart_top.v
MODSTYLE uart_top.v Normal
MODULE uart_receiver.v
MODSTYLE uart_receiver.v Normal
MODULE uart_debug_if.v
MODSTYLE uart_debug_if.v Normal
MODULE uart_transmitter.v
MODSTYLE uart_transmitter.v Normal
SYNTHESIS_TOOL Synplify
SIMULATOR_TOOL ModelSim
TOPMODULE uart_top.v