uart_3.syn

来自「vlsi UART referene, use UART0_3」· SYN 代码 · 共 23 行

JDF B
// Created by Version 7.0 
PROJECT Uart_3
DESIGN uart_3 Normal
DEVKIT LFXP10C-5F388C
ENTRY Pure Verilog HDL
MODULE uart_regs.v
MODULE uart_sync_flops.v
MODSTYLE uart_sync_flops Normal
MODULE uart_top.v
MODSTYLE uart_top Normal
MODULE uart_receiver.v
MODULE uart_debug_if.v
MODSTYLE uart_debug_if Normal
MODULE uart_defines.v
MODSTYLE uart_defines.v Normal
MODULE uart_transmitter.v
MODULE timescale.v
MODSTYLE timescale.v Normal
SYNTHESIS_TOOL Synplify
SIMULATOR_TOOL ModelSim
TOPMODULE uart_sync_flops