📄 automake.log
字号:
No replication required. 2 0h:00m:04s -2.79ns 137 / 100 3 0h:00m:04s -2.79ns 137 / 100 4 0h:00m:05s -2.79ns 137 / 100------------------------------------------------------------Net buffering Report for view:work.uart_regs(verilog):No nets needed buffering.Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:05s; Memory used current: 56MB peak: 57MB)@W: BN116 :"f:\new_uart\uart0_2\uart0_3\uart_transmitter.v":192:0:192:5|Removing sequential instance transmitter.stx_o_tmp of view:UNILIB.FDPE(PRIM) because there are no references to its outputs @W: BN132 :|Removing instance m17_1, because it is equivalent to instance m17_0Found clock uart_regs|clk with period 5.00ns ##### START OF TIMING REPORT #####[# Timing Report written on Sat Mar 07 01:35:08 2009#Top view: uart_regsRequested Frequency: 200.0 MHzWire load mode: topPaths requested: 3Constraint File(s): @N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..Performance Summary *******************Worst slack in design: -3.397 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------uart_regs|clk 200.0 MHz 133.2 MHz 5.000 7.507 -2.507 inferred Inferred_clkgroup_0System 200.0 MHz 119.1 MHz 5.000 8.397 -3.397 system default_clkgroup ======================================================================================================================Clock Relationships*******************Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack---------------------------------------------------------------------------------------------------------------------uart_regs|clk uart_regs|clk | 5.000 -2.507 | No paths - | No paths - | No paths - ===================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.Interface Information *********************Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock -------------------------------------------------------------------------------------addr_i[0] System (rising) NA 0.000 -2.330 addr_i[1] System (rising) NA 0.000 -3.393 addr_i[2] System (rising) NA 0.000 -3.397 addr_i[3] System (rising) NA 0.000 -2.240 addr_i[4] System (rising) NA 0.000 -2.240 clk NA NA NA NA NA dat_i[0] System (rising) NA 0.000 3.018 dat_i[1] System (rising) NA 0.000 3.018 dat_i[2] System (rising) NA 0.000 3.018 dat_i[3] System (rising) NA 0.000 3.018 dat_i[4] System (rising) NA 0.000 3.027 dat_i[5] System (rising) NA 0.000 3.060 dat_i[6] System (rising) NA 0.000 3.027 dat_i[7] System (rising) NA 0.000 3.027 modem_inputs[0] System (rising) NA 0.000 2.351 modem_inputs[1] System (rising) NA 0.000 2.351 modem_inputs[2] System (rising) NA 0.000 2.351 modem_inputs[3] System (rising) NA 0.000 2.351 re_i System (rising) NA 0.000 0.511 rst_i System (rising) NA 0.000 2.375 srx_pad_i NA NA NA NA NA we_i System (rising) NA 0.000 0.869 =====================================================================================Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock --------------------------------------------------------------------------------------dat_o[0] System (rising) NA 8.397 5.000 dat_o[1] uart_regs|clk (rising) NA 7.507 5.000 dat_o[2] uart_regs|clk (rising) NA 7.507 5.000 dat_o[3] System (rising) NA 8.397 5.000 dat_o[4] System (rising) NA 8.397 5.000 dat_o[5] System (rising) NA 8.397 5.000 dat_o[6] System (rising) NA 8.397 5.000 dat_o[7] System (rising) NA 8.397 5.000 dtr_pad_o uart_regs|clk (rising) NA 4.661 5.000 int_o uart_regs|clk (rising) NA 4.619 5.000 rts_pad_o uart_regs|clk (rising) NA 4.661 5.000 stx_pad_o uart_regs|clk (rising) NA 5.547 5.000 ======================================================================================##### END OF TIMING REPORT #####]---------------------------------------Resource Usage ReportPart: lfxp10c-5Register bits: 99 of 9728 (1)I/O cells: 33Details:CCU2: 14FD1P3AX: 47FD1P3AY: 4FD1S3AX: 42FD1S3AY: 5GSR: 1IB: 21INV: 5OB: 12OFS1P3DX: 1ORCALUT4: 122PFUMX: 11VHI: 1VLO: 1Finished restoring hierarchy (Time elapsed 0h:00m:05s; Memory used current: 56MB peak: 57MB)Writing Analyst data base F:\new_uart\uart0_2\uart0_3\uart_regs.srm@N: MF203 |Set autoconstraint_io Writing EDIF Netlist and constraint files@N: MF203 |Set autoconstraint_io Version 8.8L2Writing Verilog Simulation files@N: MF203 |Set autoconstraint_io Writing VHDL Simulation files@N: MF203 |Set autoconstraint_io @N: MF203 |Set autoconstraint_io Mapper successful!Process took 0h:00m:12s realtime, 0h:00m:06s cputime# Sat Mar 07 01:35:10 2009###########################################################]Done: completed successfully.
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -