uart_regs.log

vlsi UART referene, use UART0_3

#Build: Synplify for Lattice 8.8L2, Build 008R, Dec  7 2006
#install: C:\ISPTOOLS7_0\SYNPBASE
#OS: Windows XP 5.1
#Hostname: PRAVEEN-A76FCBB

#Implementation: uart0_3

#Sat Mar 07 01:34:55 2009

$ Start of Compile
#Sat Mar 07 01:34:55 2009

Synplicity Verilog Compiler, version 3.7.5, Build 161R, built Apr 17 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@I::"C:\ISPTOOLS7_0\SYNPBASE\lib\lucent\xp.v"
@I::"C:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\XP.v"
@I::"F:\new_uart\uart0_2\uart0_3\uart_3.h"
@I::"F:\new_uart\uart0_2\uart0_3\uart_receiver.v"
@W: CS141 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":102:14:102:16|Unrecognized synthesis directive was
@N: CG334 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":195:12:195:24|Read directive translate_off 
@N: CG333 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":197:12:197:23|Read directive translate_on 
@I:"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":"F:\new_uart\uart0_2\uart0_3\uart_defines.v"
@I::"F:\new_uart\uart0_2\uart0_3\uart_sync_flops.v"
@I:"F:\new_uart\uart0_2\uart0_3\uart_sync_flops.v":"F:\new_uart\uart0_2\uart0_3\timescale.v"
@I::"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v"
@N: CG334 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":151:12:151:24|Read directive translate_off 
@N: CG333 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":153:12:153:23|Read directive translate_on 
@I::"F:\new_uart\uart0_2\uart0_3\uart_regs.v"
@W: CS141 :"F:\new_uart\uart0_2\uart0_3\uart_regs.v":104:14:104:16|Unrecognized synthesis directive was
@N: CG334 :"F:\new_uart\uart0_2\uart0_3\uart_regs.v":226:12:226:24|Read directive translate_off 
@N: CG333 :"F:\new_uart\uart0_2\uart0_3\uart_regs.v":228:12:228:23|Read directive translate_on 
Verilog syntax check successful!
Selecting top level module uart_regs
@N: CG364 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":157:7:157:22|Synthesizing module uart_transmitter

@W: CG360 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":190:31:190:41|No assignment to wire tf_data_out

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":192:0:192:5|Pruning Register tf_pop 

@N: CG364 :"F:\new_uart\uart0_2\uart0_3\uart_sync_flops.v":74:7:74:21|Synthesizing module uart_sync_flops

	Tp=32'b00000000000000000000000000000001
	width=32'b00000000000000000000000000000001
	init_value=1'b1
   Generated name = uart_sync_flops_1s_1s_1
@N: CG364 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":201:7:201:19|Synthesizing module uart_receiver

@W: CG360 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|No assignment to wire rf_data_out

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rshift[7:0] 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rbit_in 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rparity 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rparity_xor 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rparity_error 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rf_data_in[10:0] 

@N: CG364 :"F:\new_uart\uart0_2\uart0_3\uart_regs.v":236:7:236:15|Synthesizing module uart_regs

@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_regs.v":402:17:402:27|*Input sys_clk_i to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_regs.v":434:14:434:21|*Input sys_clk_i to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@N: CL201 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Trying to extract state machine for register rstate
Extracted state machine for register rstate
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
@W: CL234 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":206:12:206:14|Input port bits <7 to 4> of lcr[7:0] are unused

@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":214:34:214:41|*Input rf_count[4] to this expression [not] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":214:34:214:41|*Output rf_count has undriven bits - a simulation mismatch is possible 
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|*Output rf_data_out has undriven bits - a simulation mismatch is possible 
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":217:10:217:21|*Output rf_error_bit has undriven bits - a simulation mismatch is possible 
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":216:10:216:19|*Output rf_overrun has undriven bits - a simulation mismatch is possible 
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":210:9:210:16|Input rx_reset is unused
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":211:12:211:19|Input lsr_mask is unused
@N: CL201 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":192:0:192:5|Trying to extract state machine for register tstate
@W: CL209 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":161:21:161:23|Input port bit <7> of lcr[7:0] is unused

@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":225:24:225:40|*Input tf_count[4:0] to this expression [ror] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":194:2:194:3|*Input tf_data_out[7:1] to this expression [mux] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":208:1:208:4|*Input tf_data_out[0] to this expression [pmux] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":169:40:169:47|*Output tf_count has undriven bits - a simulation mismatch is possible 
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":162:16:162:22|Input tf_push is unused
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":163:21:163:26|Input data_i is unused
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":165:16:165:23|Input tx_reset is unused
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":166:16:166:23|Input lsr_mask is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Mar 07 01:34:57 2009

###########################################################]
Synplicity Generic Technology Mapper, Version 8.8.0, Build 018R, Built Apr 17 2007 19:29:01
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8L2
@N: MF249 |Running in 32-bit mode.


@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_transmitter.v":169:40:169:47|tristate driver tf_count_5 on net tf_count_5 has its enable tied to GND (module uart_transmitter) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_transmitter.v":169:40:169:47|tristate driver tf_count_4 on net tf_count_4 has its enable tied to GND (module uart_transmitter) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_transmitter.v":169:40:169:47|tristate driver tf_count_3 on net tf_count_3 has its enable tied to GND (module uart_transmitter) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_transmitter.v":169:40:169:47|tristate driver tf_count_2 on net tf_count_2 has its enable tied to GND (module uart_transmitter) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_transmitter.v":169:40:169:47|tristate driver tf_count_1 on net tf_count_1 has its enable tied to GND (module uart_transmitter) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":216:10:216:19|tristate driver rf_overrun on net rf_overrun has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":217:10:217:21|tristate driver rf_error_bit on net rf_error_bit has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_9 on net rf_data_out_9 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_8 on net rf_data_out_8 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_7 on net rf_data_out_7 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_6 on net rf_data_out_6 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_5 on net rf_data_out_5 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_4 on net rf_data_out_4 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_3 on net rf_data_out_3 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_2 on net rf_data_out_2 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_11 on net rf_data_out_11 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_10 on net rf_data_out_10 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|tristate driver rf_data_out_1 on net rf_data_out_1 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":214:34:214:41|tristate driver rf_count_5 on net rf_count_5 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":214:34:214:41|tristate driver rf_count_4 on net rf_count_4 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":214:34:214:41|tristate driver rf_count_3 on net rf_count_3 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":214:34:214:41|tristate driver rf_count_2 on net rf_count_2 has its enable tied to GND (module uart_receiver) 
@W: MO111 :"f:\new_uart\uart0_2\uart0_3\uart_receiver.v":214:34:214:41|tristate driver rf_count_1 on net rf_count_1 has its enable tied to GND (module uart_receiver) 
@W: MO111 :|tristate driver tf_count_t[4] on net tf_count[4] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver tf_count_t[3] on net tf_count[3] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver tf_count_t[2] on net tf_count[2] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver tf_count_t[1] on net tf_count[1] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver tf_count_t[0] on net tf_count[0] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_overrun_t on net rf_overrun has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_error_bit_t on net rf_error_bit has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_data_out_t[9] on net rf_data_out[9] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_data_out_t[8] on net rf_data_out[8] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_data_out_t[7] on net rf_data_out[7] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_data_out_t[6] on net rf_data_out[6] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_data_out_t[5] on net rf_data_out[5] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_data_out_t[4] on net rf_data_out[4] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_data_out_t[3] on net rf_data_out[3] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_data_out_t[10] on net rf_data_out[10] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_count_t[4] on net rf_count[4] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_count_t[3] on net rf_count[3] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_count_t[2] on net rf_count[2] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_count_t[1] on net rf_count[1] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver rf_count_t[0] on net rf_count[0] has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver lsr4_t on net lsr4 has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver lsr3_t on net lsr3 has its enable tied to GND (module uart_regs) 
@W: MO111 :|tristate driver lsr2_t on net lsr2 has its enable tied to GND (module uart_regs) 
Automatic dissolve at startup in view:work.uart_regs(verilog) of i_uart_sync_flops(uart_sync_flops_1s_1s_1)
RTL optimization done.