uart_3.tcl

vlsi UART referene, use UART0_3

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# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 00:51:30 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 00:52:04 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 00:52:21 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 00:52:34 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:52:34 ###########


########## Tcl recorder starts at 03/07/09 00:52:52 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 00:53:11 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:53:11 ###########


########## Tcl recorder starts at 03/07/09 00:54:39 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 00:54:48 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:54:48 ###########


########## Tcl recorder starts at 03/07/09 00:54:58 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 00:55:04 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 00:56:30 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:56:30 ###########


########## Tcl recorder starts at 03/07/09 00:57:33 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 00:58:04 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 01:01:42 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_regs.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 01:02:19 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_regs.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 01:04:06 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_regs.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 01:20:05 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_transmitter.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 01:21:01 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_transmitter.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 03/07/09 01:24:19 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_transmitter.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 01:24:19 ###########


########## Tcl recorder starts at 03/07/09 01:28:27 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_receiver.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 01:28:27 ###########


########## Tcl recorder starts at 03/07/09 01:32:26 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_receiver.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 01:32:26 ###########


########## Tcl recorder starts at 03/07/09 01:33:55 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_receiver.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 01:33:55 ###########


########## Tcl recorder starts at 03/07/09 01:34:17 ##########

# Commands to make the Process: 
# Synplify Synthesize Verilog File
if [catch {open uart_3.rvp w} rspFile] {
	puts stderr "Cannot create response file uart_3.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=uart_3.sty
PROJECT=uart_3
ENTRY=Pure Verilog HDL
WORKING_PATH=$proj_dir
MODULE=uart_top
TOP_FILE=uart_top.v
EDF_FILE_LIST=uart_regs.v uart_defines.v uart_transmitter.v uart_top.v uart_sync_flops.v Uart_3.h timescale.v uart_receiver.v uart_debug_if.v
VHDL_FILE_LIST=
VERILOG_FILE_LIST=uart_3.h uart_receiver.v uart_sync_flops.v uart_transmitter.v uart_regs.v
DEVICEPART=LFXP10C-5F388C
"
	close $rspFile
}
if [catch {open uart_regs.cmd w} rspFile] {
	puts stderr "Cannot create response file uart_regs.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: uart_3.sty
PROJECT: uart_regs
WORKING_PATH: \"$proj_dir\"
MODULE: uart_regs
VERILOG_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/XP.v\" uart_3.h uart_receiver.v uart_sync_flops.v uart_transmitter.v uart_regs.v
OUTPUT_FILE_NAME: uart_regs
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:  3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:  0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -rem -e uart_regs -target LATTICE-XP -part LFXP10C"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 01:34:17 ###########


########## Tcl recorder starts at 03/07/09 01:34:47 ##########

# Commands to make the Process: 
# Synthesized EDIF File
if [catch {open uart_3.rvp w} rspFile] {
	puts stderr "Cannot create response file uart_3.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=uart_3.sty
PROJECT=uart_3
ENTRY=Pure Verilog HDL
WORKING_PATH=$proj_dir
MODULE=uart_top
TOP_FILE=uart_top.v
EDF_FILE_LIST=uart_regs.v uart_defines.v uart_transmitter.v uart_top.v uart_sync_flops.v Uart_3.h timescale.v uart_receiver.v uart_debug_if.v
VHDL_FILE_LIST=
VERILOG_FILE_LIST=uart_3.h uart_receiver.v uart_sync_flops.v uart_transmitter.v uart_regs.v
DEVICEPART=LFXP10C-5F388C
"
	close $rspFile
}
if [catch {open uart_regs.cmd w} rspFile] {
	puts stderr "Cannot create response file uart_regs.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: uart_3.sty
PROJECT: uart_regs
WORKING_PATH: \"$proj_dir\"
MODULE: uart_regs
VERILOG_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/XP.v\" uart_3.h uart_receiver.v uart_sync_flops.v uart_transmitter.v uart_regs.v
OUTPUT_FILE_NAME: uart_regs
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -5
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:  3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:  0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -rem -e uart_regs -target LATTICE-XP -part LFXP10C"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 01:34:47 ###########