uart_3.tcl

vlsi UART referene, use UART0_3

########## Tcl recorder starts at 03/06/09 23:48:53 ##########

set version "7.0"
set proj_dir "F:/NEW_UART/UART0_2/UART0_3"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue}
	if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]
set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end]
regsub -all "\"" $fpga_bin "" fpga_bin
set fpga_bin [file join $fpga_bin]

if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$fpga_bin;$env(PATH)" }

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_regs.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_defines.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_transmitter.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_sync_flops.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"timescale.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_receiver.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_debug_if.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/06/09 23:48:53 ###########


########## Tcl recorder starts at 03/06/09 23:52:07 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/06/09 23:52:07 ###########


########## Tcl recorder starts at 03/06/09 23:55:34 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/06/09 23:55:34 ###########


########## Tcl recorder starts at 03/06/09 23:56:11 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/06/09 23:56:11 ###########


########## Tcl recorder starts at 03/06/09 23:56:42 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/06/09 23:56:42 ###########


########## Tcl recorder starts at 03/06/09 23:58:13 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/06/09 23:58:13 ###########


########## Tcl recorder starts at 03/07/09 00:08:38 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:08:38 ###########


########## Tcl recorder starts at 03/07/09 00:09:24 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:09:24 ###########


########## Tcl recorder starts at 03/07/09 00:11:50 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:11:50 ###########


########## Tcl recorder starts at 03/07/09 00:16:30 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:16:30 ###########


########## Tcl recorder starts at 03/07/09 00:22:58 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:22:58 ###########


########## Tcl recorder starts at 03/07/09 00:23:15 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:23:15 ###########


########## Tcl recorder starts at 03/07/09 00:23:24 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:23:24 ###########


########## Tcl recorder starts at 03/07/09 00:25:32 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:25:32 ###########


########## Tcl recorder starts at 03/07/09 00:25:41 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:25:41 ###########


########## Tcl recorder starts at 03/07/09 00:26:18 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:26:18 ###########


########## Tcl recorder starts at 03/07/09 00:26:35 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:26:35 ###########


########## Tcl recorder starts at 03/07/09 00:27:12 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:27:12 ###########


########## Tcl recorder starts at 03/07/09 00:39:05 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:39:05 ###########


########## Tcl recorder starts at 03/07/09 00:41:38 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:41:38 ###########


########## Tcl recorder starts at 03/07/09 00:42:20 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:42:20 ###########


########## Tcl recorder starts at 03/07/09 00:42:48 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:42:48 ###########


########## Tcl recorder starts at 03/07/09 00:44:32 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 03/07/09 00:44:32 ###########


########## Tcl recorder starts at 03/07/09 00:44:47 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"uart_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_3.h -setting uart_3.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}