uart_regs.tlg

vlsi UART referene, use UART0_3

Selecting top level module uart_regs
@N: CG364 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":157:7:157:22|Synthesizing module uart_transmitter

@W: CG360 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":190:31:190:41|No assignment to wire tf_data_out

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":192:0:192:5|Pruning Register tf_pop 

@N: CG364 :"F:\new_uart\uart0_2\uart0_3\uart_sync_flops.v":74:7:74:21|Synthesizing module uart_sync_flops

	Tp=32'b00000000000000000000000000000001
	width=32'b00000000000000000000000000000001
	init_value=1'b1
   Generated name = uart_sync_flops_1s_1s_1
@N: CG364 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":201:7:201:19|Synthesizing module uart_receiver

@W: CG360 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|No assignment to wire rf_data_out

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rshift[7:0] 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rbit_in 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rparity 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rparity_xor 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rparity_error 

@W: CL169 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Pruning Register rf_data_in[10:0] 

@N: CG364 :"F:\new_uart\uart0_2\uart0_3\uart_regs.v":236:7:236:15|Synthesizing module uart_regs

@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_regs.v":402:17:402:27|*Input sys_clk_i to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_regs.v":434:14:434:21|*Input sys_clk_i to this expression [instance] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@N: CL201 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":262:0:262:5|Trying to extract state machine for register rstate
Extracted state machine for register rstate
State machine has 11 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
@W: CL234 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":206:12:206:14|Input port bits <7 to 4> of lcr[7:0] are unused

@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":214:34:214:41|*Input rf_count[4] to this expression [not] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":214:34:214:41|*Output rf_count has undriven bits - a simulation mismatch is possible 
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":215:34:215:44|*Output rf_data_out has undriven bits - a simulation mismatch is possible 
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":217:10:217:21|*Output rf_error_bit has undriven bits - a simulation mismatch is possible 
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":216:10:216:19|*Output rf_overrun has undriven bits - a simulation mismatch is possible 
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":210:9:210:16|Input rx_reset is unused
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_receiver.v":211:12:211:19|Input lsr_mask is unused
@N: CL201 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":192:0:192:5|Trying to extract state machine for register tstate
@W: CL209 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":161:21:161:23|Input port bit <7> of lcr[7:0] is unused

@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":225:24:225:40|*Input tf_count[4:0] to this expression [ror] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":194:2:194:3|*Input tf_data_out[7:1] to this expression [mux] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL156 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":208:1:208:4|*Input tf_data_out[0] to this expression [pmux] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W: CL157 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":169:40:169:47|*Output tf_count has undriven bits - a simulation mismatch is possible 
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":162:16:162:22|Input tf_push is unused
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":163:21:163:26|Input data_i is unused
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":165:16:165:23|Input tx_reset is unused
@W: CL159 :"F:\new_uart\uart0_2\uart0_3\uart_transmitter.v":166:16:166:23|Input lsr_mask is unused