uart_regs.srd

vlsi UART referene, use UART0_3

f "noname"; #file 0
f "c:\isptools7_0\synpbase\lib\lucent\xp.v"; #file 1
f "c:\isptools7_0\ispcpld\..\cae_library\synthesis\verilog\xp.v"; #file 2
f "f:\new_uart\uart0_2\uart0_3\uart_3.h"; #file 3
f "f:\new_uart\uart0_2\uart0_3\uart_receiver.v"; #file 4
f "f:\new_uart\uart0_2\uart0_3\uart_defines.v"; #file 5
f "f:\new_uart\uart0_2\uart0_3\uart_sync_flops.v"; #file 6
f "f:\new_uart\uart0_2\uart0_3\timescale.v"; #file 7
f "f:\new_uart\uart0_2\uart0_3\uart_transmitter.v"; #file 8
f "f:\new_uart\uart0_2\uart0_3\uart_regs.v"; #file 9
VNAME 'work.uart_regs.verilog'; # view id 0
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